PEB22320 Просмотр технического описания (PDF) - Infineon Technologies

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производитель

PEB22320

Primary Rate Access Clock Generator and Transceiver

Infineon Technologies 

PEB 22320

Features

1.3 System Integration

Figure 1 shows the architecture of a primary access board for data transmission. It

exhibits the following functions:

– Line Interface (PEB 22320, PRACT)

– Clock and Data Recovery (PEB 22320, PRACT)

– Jitter Attenuation (PEB 22320, PRACT)

– Clock Generation (PEB 22320, PRACT)

– Coding/Decoding (PEB 2035, ACFA)

– Framing (PEB 2035, ACFA)

– Elastic Buffer (PEB 2035, ACFA)

– Multichannel Protocol Controller (PEB 20320, MUNICH32)

– System Adaptation (PEB 20320, MUNICH32)

– µP Interface (all devices)

MPU

Memory

PC

Interface

MUNICH32

PEB 20320

TCLK/RCLK TSP/RSP

8 kHz

2.048 MHz

ACFA

PEB 2035

PRACT

PEB 22320

SYPQ SCLK

CLK4M FSC FSC CLK2M

8 kHz

4.096 MHz

ITS04875

Figure 1

Architecture of the PRACT

Semiconductor Group

10

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