ADC150C Просмотр технического описания (PDF) - Thaler Corporation

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ADC150C

Programmable Integrating A/D Converter

Thaler Corporation 

CONNECTING THE ADC150

POWER SUPPLIES

MODE CONTROL (Pin 25)

The power supply lines are connected to pins 4-7. This line is used to program the ADC150. The

Pin 4 is -15V, pin 5 is +15V, pin 6 is +5V and pin 7 mode control byte (8 bit) is placed on the data bus.

is GND.

Pin 25 is then set to logic high, pin 21 is pulsed low

to accept the control byte. Pin 22 is then pulsed low

OUTPUT DATA LINES

and held low until the status lines return high

The output data is available in byte form on pins (~2ms). Pin 21 is then pulsed high and pin 25 is

13-20. Pin 20 is the Most Significant Bit and pin 13 then returned to logic low. The ADC150 has now

the Least Significant Bit. The data lines go to a high been reset to the new parameters. See figure 6 for

impedance state when the Output Enable line is at a timing diagrams.

logic one level.

The mode control byte is defined as follows:

Bits 7 and 6 - unused

OUTPUT ENABLE (PIN 21)

Bits 5 and 4 - 00 Pin 39 signal input, autozero*

Data is placed on the Output Data Lines by a logic

01 Pin 38 signal input

zero on this line. See figure 2 for data output Bit 3

- 0 60 Hz.*

format.

1 50 Hz.

Bits 2,1, 0 - 001 18 Bit

CONVERT (Pin22)

This line is used to initiate a conversion cycle and

to retrieve the output data. The status lines indicate

which function will be executed. The first pulse

010 20 Bit

011 22 Bit*

100 24 Bit

* Factory default settings

(transition from logic one to logic zero) starts the

conversion cycle. Two subsequent pulses are used AUTO-ZERO / RESET (Pin 29)

to place the lower two bytes on the Output Data A logic zero on this input will autozero the ADC150

Lines. See figure 4 for timing diagram.

by internally connecting the analog high to analog

low. Since the µP is reset, the ADC150 reverts to

STATUS LINES (Pins 23, 24)

These lines indicate the present state of the ADC.

When the Convert line receives the first pulse in a

conversion cycle the Status Lines go to logic zero,

indicating that a conversion cycle is in progress.

the factory default settings in the EPROM (ie.

22bits, 60Hz, pin 39 analog high). To select a

mode different than the default settings, the mode

control must be set after auto zero. See figure 3 for

timing diagrams.

When the conversion is complete the

microprocessor places the MSB of the output data INTEGRATION CAPACITOR (Pin 34, 35)

in the output buffer and then raises S0 to a logic

one, indicating that the MSB at the output data is

available in the output buffer. When the Convert

Line is pulsed again the middle byte of the output

A 0.68 µF polystyrene or Mylar must be connected

to these pins. Lead length should be as short as

possible and not exceed 2".

data is placed in that output buffer and S1 changes

to logic one and S0 to logic zero. The third pulse

places the LSB of the output data in the buffer and

both status lines go to the logic one. The converter

is now ready for the next conversion cycle. See

figure 5 for timing diagrams.

The table below shows a summary of the status

ANALOG INPUTS (Pin 39, 40)

Both analog inputs are buffered by op-amps and

have a common mode rejection of approximately

80dB minimum. To maintain the full accuracy at the

ADC it is recommended to keep the input to analog

low to less than 0.1VDC.

code.

S1 S0

0 0 Conversion in process.

0 1 Conversion complete. MSB in output.

1 0 Middle byte in output register.

1 1 LSB in output. Ready for next conversion.

ADC150DS REV. F MAR 00

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