SI9993CS Просмотр технического описания (PDF) - Vishay Semiconductors

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SI9993CS

12-V VCM/Spindle Motor Driver for Large Capacity HDD

Vishay Semiconductors 

Si9993CS

Vishay Siliconix

FUNCTIONAL DESCRIPTION

Voice Coil Motor Driver

The VCM driver provides all necessary control functions, for a

linear transconductance stage, including a motor current

sense amplifier, a loop compensation amplifier and a 3-A

power amplifier featuring two Si9942’s (external) in a full

H-bridge configuration. The output half-bridge operates in the

Class B mode during seeking. The track following mode is

primarily a function of an onboard class AB bipolar driver. The

output crossover distortion is kept to a minimum by the

combined BiCMOS driver. Two external components (R3 and

C3) are required to set the bandwidth of the full

transconductance stage. For greater flexibility in interfacing to

the external D/A converter, a DAC reference, an input level

shifting amplifier and gain select are included. To minimize

power dissipation of the power stage during the seek

operation, the VCM driver may also be re-configured (via Bit

D3/2 of REG0, see Table 2) into a constant frequency

Pulse-Width-Modulated (PWM) driver. No additional external

components are required for this useful option. The head

retract circuitry can be activated by an undervoltage condition,

an external command via serial port, or direct control via the

RESETVCM pin. The retract voltage clamp is programmable

from 0.4 to 1.2 V.

External VCM DAC Operation

The VCM driver of the Si9993CS is designed to interface to an

external DAC with an output range from 0.1 V to 4.5 V and

uses the internal 2.3 V as the mid-point reference (signal

common). Therefore, a differential input of up to ±2.2 V may

be accepted. Depending on the type of DAC chosen, either

VREF/2 (+2.3 V) or VREF (+5.0 V) can be used as the DAC

reference. The inaccuracy of the mid-point reference may be

eliminated through calibration by disabling the VCM driver

[D7/D6 (REG0) = 00 or 01] and digitizing the VCM current

sense output (IVCMS). The digitized value is to be stored in

the ASIC or DSP as the VCM current zero scale correction

factor. A differential level shift amplifier has been added

between the internal 12-V current sense amplifier and the

IVCMS pin such that an external ADC operating from a 5-V

power supply may be used directly.

Spindle Motor Driver

The spindle driver powers a three-phase brushless dc motor

in open drive configuration and utilizing a Hall sensor-less

commutation technique. To minimize power stress on the

three Si9942 (external) half-bridges, the driver operates in full

time, constant off-time or variable frequency, PWM current

mode. A proprietary BEMF sensing technique, consisting of a

filter and a programmable EMF zero crossing comparator and

an intelligent commutation delay generator, is used to derive

the proper commutation zero crossing in the presence of

severe PWM noise. The start-up of the motor is initiated by

the microprocessor through the STEPCLK and ENCOM pins.

This arrangement allows the user to tailor a start-up algorithm

for any given drive. As shown in Table 2, the microprocessor

may strobe the STEPCLK pin to force a new motor state

sequentially. Multiple clocking will allow any undesired state to

be bypassed. At an empirically determined time, the internal

commutation clock generation loop may be closed by forcing

ENCOM high. For complete interfacing to the

microprocessor’s PWM DAC, a level shifting amplifier,

accepting a wide input range (via D5/D4 or REG5), is also

included on chip. To minimize acoustic or EMI noise, the slew

rate of the output drivers (via HSA/B/C and LSA/B/C) may be

programmed by an external resistor connected through the

SRADJ pin. Additional software slew rate controls are

available through D2/D1 of REG4.

The speed control signal from the external micro or DSP is fed

to the output PWM modulator via an external DAC and the

onboard buffer/level shifter. The interface is designed to work

with either PWM or linear DAC. Should a PWM DAC be

chosen, a stand-alone digital buffer is available to level shift

the 5-V signal from the PWM timer (referred to VDD) to a

supply independent signal (referred to VREF), before it is fed to

the external RC low pass filter.

Adaptive Commutation Delay Operation1

Inside the spindle controller of Si9993CS, the desired

30 electrical degrees (or 90 degrees for a single phase) of

commutation delay is generated by sensing the motor

back-emf zero crossing at the unenergized winding with a

current-controlled transconductance amplifier and charging

an internal capacitor to be programmable threshold with the

output current of the amplifier. The delay time generated is

proportional to the speed of the motor because the charging

current is derived from a motor frequency to current converter.

This proprietary analog timing generator, combined with the

external low-pass filter (three 200-kΩ resistors), provide

excellent immunity to the highly unstable PWM noise. The

resulting motor once-around jitter time is comparable to that of

a linear drive system. Furthermore, the highly integrated

nature of the design has eliminated all external capacitors,

representing a significant savings in cost and board space.

For maximum flexibility, D2/D1 of REG5 may be used to

program the frequency to current converter filter bandwidth.

For very high performance drive, D7/D2 or REG3 programs

the commutation delay threshold in both negative (phase

advance up to 23.5°) and positive (phase delay up to 7.5°)

directions.

S-60752–Rev. A, 05-Apr-99

10

FaxBack 408-970-5600, request 70653

www.siliconix.com

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