AD7545 Просмотр технического описания (PDF) - Intersil
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AD7545 Datasheet PDF : 8 Pages
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AD7545
Electrical Specifications
PARAMETER
TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified (Continued)
VDD = +5V (NOTE 7)
VDD = +15V (NOTE 7)
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNITS
REFERENCE INPUT
Input Resistance (Pin 19 to GND)
Input Resistance
TC = -300ppm/oC (Typ)
7
-
-
7
-
-
kΩ
Typical Input Resistance = 11kΩ
-
-
25
-
-
25
kΩ
DIGITAL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
Input Capacitance
DB0 -
DB11
VIN = 0 or VDD (Note 6)
VIN = 0 (Note 4)
2.4
-
-
-
-
13.5
V
-
-
0.8
-
-
1.5
V
±1
-
±10
±1
-
±10
µA
-
-
7
-
-
7
pF
WR, CS VIN = 0 (Note 4)
SWITCHING CHARACTERISTICS (Note 4)
-
-
20
-
-
20
pF
Chip Select to Write Setup Time, tCS See Figure 1
380
200
-
200
120
-
ns
Chip Select to Write Hold Time, tCH See Figure 1
0
-
-
0
-
-
ns
Write Pulse Width, tWR
tCS ≥ tWR , tCH ≥ 0, See Figure 1 400
175
-
240
100
ns
Data Setup Time, tDS
See Figure 1
210
100
-
120
60
-
ns
Data Hold Time, tDH
See Figure 1
10
-
-
10
-
-
ns
POWER SUPPLY CHARACTERISTICS
IDD
All Digital Inputs VIL or VIH
-
-
2
-
-
2
mA
All Digital Inputs 0V or VDD
-
100
500
-
100
500
µA
All Digital Inputs 0V or VDD
-
10
-
-
10
-
µA
NOTES:
2. Temperature Ranges as follows: J, K versions: 0oC to 70oC
TA = 25oC for TYP Specifications. MIN and MAX are measured over the specified operating range.
3. This includes the effect of 5ppm maximum gain TC.
4. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
5. DB0 - DB11 = 0V to VDD or VDD to 0V.
6. Logic inputs are MOS gates. Typical input current (25oC) is less than 1nA.
7. Typical values are not guaranteed but reflect mean performance specification. Specifications subject to change without notice.
Timing Diagrams
CHIP
SELECT
WRITE
DATA IN
(DB0 - DB11)
tCH
tCS
tWR
tDH
tDS
DATA VALID
VDD
0
VDD
0
VDD
0
CHIP
SELECT
WRITE
DATA IN
(DB0 - DB11)
tCH
tCS
tWR
tDH
tDS
DATA VALID
VDD
0
VDD
0
VDD
0
FIGURE 1A. TYPICAL WRITE CYCLE
FIGURE 1B. PREFERRED WRITE CYCLE
FIGURE 1. WRITE CYCLE TIMING DIAGRAM
3
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