HIP1015 Просмотр технического описания (PDF) - Intersil
Номер в каталоге
Компоненты Описание
производитель
HIP1015 Datasheet PDF : 9 Pages
| |||
Simplified Block Diagram
HIP1015,HIP1016
ISET
ISEN
GATE
VSS
10µA
18V
-
+
UV
+
VREF
-
VDD
+
-
+
POR
8V
-
QN R
R
QS
ENABLE
12V
OC +
-
7.5k
CLIM
FALLING
EDGE
DELAY
ENABLE
-
+
WOCLIM
20µA
18V
10µA
+-
+
1.86V
-
RISING
EDGE
PULSE
PWRON
PGOOD
CTIM
VDD
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
SYMBOL
ISET
ISEN
GATE
VSS
VDD
CTIM
PGOOD
PWRON
FUNCTION
DESCRIPTION
Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor
External FET Gate Drive Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
Pin
sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (HIP1015) and to
VDD (HIP1016) by a 10µA current source.
Chip Return
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated VSS +12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out (in seconds) = 93kΩ x CTIM (Farads).
Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output is not within specification.
Power ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high or is open. After a current limit time out, the chip is reset by a low level signal applied to
this pin. This input has 20µA pull up capability
2
Share Link: 