SPT7938SIR Просмотр технического описания (PDF) - Signal Processing Technologies

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SPT7938SIR

12-BIT, 40 MSPS, 170 mW A/D CONVERTER

Signal Processing Technologies 

Figure 2 – Typical Interface Circuit

CLK IN

+A5

FB2

+

FB3

+

AIN

+A5

U1

+

TK11240B

Ext VREF

(+4 V)

DOVSS

DVSS

CLK

OTR

D11

D10

Out of Range Bit

MSB

DVDD

D9

AVDD

D8

AVSS

D7

VINR

D6

VIN

D5

RVSS

D4

VRHS

D3

VRHF

D2

VRLF

D1

VRLS

D0

LSB

28 EN

DOVDD 1

FB1

+D3/5V

+D3/5V

+A5

+D3/5

+

+

10

10

+A5 AGND

Notes:

1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad

surface-mount chip capacitors. They need to be placed as close to the pin as possible.

2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors.

3) FB1, FB2 and FB3 are ferrite beads. Place FB1 as close to the SPT7938 as possible.

4) U1 is a TOKO regulator, TK112XXB. XX is the regulated output voltage ranging from

1.3 V to 4.8 V with 100 mV increment. For example, TK11240B is a 4.0 V regulator.

+D3/5

DGND

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 2 shows the typical inter-

face requirements when using the SPT7938 in normal

circuit operation. The following sections provide descrip-

tions of the major functions and outline critical performance

criteria to consider for achieving the optimal device

performance.

POWER SUPPLIES AND GROUNDING

SPT suggests that both the digital (DVDD) and the analog

(AVDD) supply voltages on the SPT7938 be derived from a

single analog supply as shown in figure 2. A separate digital

supply should be used for the digital output driver supply

(OVDD) and all interface circuitry. SPT suggests using this

power supply configuration to prevent a possible latch-up

condition on power up. In addition, the power supplies must

be powered up before the analog input is applied.

SPT

5

SPT7938

5/24/00

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