HI5808EVAL1 Просмотр технического описания (PDF) - Intersil

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HI5808EVAL1

12-Bit, 9MSPS A/D Converter

Intersil 

HI5808

Pin Descriptions

PIN NO.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

NAME

CLK

DVCC1

DGND1

DVCC1

DGND1

AVCC

AGND

VIN+

VIN-

VDC

VROUT

VRIN

AGND

AVCC

D11

D10

D9

D8

D7

D6

DGND2

DVCC2

D5

D4

D3

D2

D1

D0

DESCRIPTION

Sample Clock Input.

Digital Supply (5.0V).

Digital Ground.

Digital Supply (5.0V).

Digital Ground.

Analog Supply (5.0V).

Analog Ground.

Positive Analog Input.

Negative Analog Input.

DC Bias Voltage Output.

Reference Voltage Output.

Reference Voltage Input.

Analog Ground.

Analog Supply (5.0V).

Data Bit 11 Output (MSB).

Data Bit 10 Output.

Data Bit 9 Output.

Data Bit 8 Output.

Data Bit 7 Output.

Data Bit 6 Output.

Digital Output Ground.

Digital Output Supply (3.0V to 5.0V).

Data Bit 5 Output.

Data Bit 4 Output.

Data Bit 3 Output.

Data Bit 2 Output.

Data Bit 1 Output.

Data Bit 0 Output (LSB).

Detailed Description

Theory of Operation

The HI5808 is a 12-bit fully differential sampling pipeline A/D

converter with digital error correction. Figure 14 depicts the

circuit for the front end differential-in-differential-out sample-

and-hold (S/H). The switches are controlled by an internal

clock which is a non-overlapping two phase signal, φ1 and φ2,

derived from the master clock. During the sampling phase,

φ1, the input signal is applied to the sampling capacitors,

CS. At the same time the holding capacitors, CH , are

discharged to analog ground. At the falling edge of φ1 the

input signal is sampled on the bottom plates of the sampling

capacitors. In the next clock phase, φ2, the two bottom

plates of the sampling capacitors are connected together

and the holding capacitors are switched to the op-amp

output nodes. The charge then redistributes between CS

and CH completing one sample-and-hold cycle. The output

is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-

hold function but will also convert a single-ended input to a

fully-differential output for the converter core. During the

sampling phase, the VIN pins see only the on-resistance of a

switch and CS . The relatively small values of these

components result in a typical full power input bandwidth of

100MHz for the converter.

VIN+

φ1

CS

φ2

φ 1 CH

-

+

+-

VIN-

φ1

CS

φ1

CH

φ1

VOUT +

VOUT -

φ1

FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD

As illustrated in the functional block diagram and the timing

diagram in Figure 1, three identical pipeline subconverter

stages, each containing a four-bit flash converter, a four-bit

digital-to-analog converter and an amplifier with a voltage gain

of 8, follow the S/H circuit with the fourth stage being only a 4-

bit flash converter. Each converter stage in the pipeline will be

sampling in one phase and amplifying in the other clock phase.

Each individual sub-converter clock signal is offset by 180

degrees from the previous stage clock signal, with the result

that alternate stages in the pipeline will perform the same

operation.

The digital output of each of the three identical 4-bit

subconverter stages is a four-bit digital word containing a

supplementary bit to be used by the digital error correction

logic. The output of each subconverter stage is input to a digital

delay line which is controlled by the internal sampling clock.

The function of the digital delay line is to time align the digital

outputs of the three identical four-bit subconverter stages with

the corresponding output of the fourth stage flash converter

before applying the sixteen bit result to the digital error

correction logic. The digital error correction logic uses the

supplementary bits to correct any error that may exist before

generating the final twelve bit digital data output of the

converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus on the 3rd cycle of the clock after the analog

sample is taken. This time delay is specified as the data

latency. After the data latency time, the digital data

representing each succeeding analog sample is output on

the following clock pulse. The digital output data is

synchronized to the external sampling clock with an output

latch. The output of the digital error correction circuit is

available in offset binary format (see Table 1, A/D Code

Table).

8

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