LND-TRN902 Просмотр технического описания (PDF) - Linear Dimensions Semiconductor

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LND-TRN902

PLL-FREQUENCY SYNTHESIZER

Linear Dimensions Semiconductor 

PLL-FREQUENCY SYNTHESIZER PROPOSED DATA SHEET

Pin Definitions and Functions

Pin No. Symbol Function

1

RFI Reference Fre quenc y

High sensitivity preamplifier input for the r-counter. The input can be AC-coupled for small input signals or DC-coupled for

large input signals.

2

VSS Ground for the digital logic

3

EN 3-Wire Interface: Enable

Enable line of the serial interface with internal pull-up resistor. When EN = H, the input signals CLK and DATA are internally

disabled. When EN = L, the received data is transferred to the latches on the positive edge of the EN-signal.

4

DATA 3-Wire Interface: Data

Serial data input with internal pull-up resistor. The last two bits before the EN-signal define the destination address.

5

CLK 3-Line Interface : Clock

Clock line with internal pull-up resistor. The serial data is read into the internal shift register on the positive edge (see pulse

diagram for serial data control)

6

VDD Positive supply voltage for the digital logic

7

MOD Modulus Control

for external dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the a-counter has reached

its set value, MOD switches to high. When the n-counter has reached its set value, MOD switches to low and the cycle starts

again. When the prescaler has the counter factor P or P+1 (P for MOD = H, P+1 for MOD =L), the overall scaling factor is NP

+ A. The value of the a-counter must be smaller than that of the n-counter. The trigger edge of the modulus signal to the input

signal can be selected (see programming tables and MOD A, B) according to the needs of the prescaler. In single modulus

operation and for standby operation in dual modulus operation, the output is low.

8

VFI VCO-Frequenc y

High sensitivity preamplifier input for the n-counter. The input can be AC-coupled for small input signals or DC-coupled for

large input signals.

9

AVSS Ground for the analog logic

(Note: The pins VDD and AVDD and also pins VSS and AVSS must have the same su pp ly volta ge.)

10

PD Phase Detector

Tristate charge pump output. The level of the charge pump output current can be programmed using the digital interface.

frequency DVFI < DRFI

p-channel current source active

frequency DVFI > DRFI

n-channel current source active

frequency DVFI = DRFI and PLL locked PD-output is tristate

standby mode

PD-output is tristate

The polarity of the output signals of the phase detector can be programmed.

11 AVDD Positive supply voltage for the analog logic

(Note: The pins VDD and AVDD and also pins VSS and AVSS must have the same su pp ly volta ge.)

12

PO1 Pro grammable Out put

for the signals DRFIN, PHIV, PHIVN and PROBIT. (DRFIN, DVFIN, PHIVN are the inverted signals of DRFI, DVFI, PHIV.)

13

PO2 Pro grammable I/O-Pin

for the output signals DVFI, PHIR and the input signal IREF

- The signals PHIR and PHIV are the digital output signals of the phase and frequency detector for use with external active

current sources.

- The signals DRFIN and DVFIN are the scaled down signals of the reference frequency and VCO-frequency.

- The programmed bit PROBIT is assigned to the PO1 output in the internal charge pump mode. The standby mode does

not affect this function.

- In the internal charge pump mode the input signal IREF determines the value of the PD-output current.

14

LD Lock Detector (open drain )

Unipolar output of the phase detector in the form of a pulse-width modulated signal. The LD-pulse width corresponds to the

phase difference. In the locked state the LD-signal is at H-level. In standby mode the output is resistive.

Linear Dimensions, Inc. 445 East Ohio Street, Chicago, IL 60611 p 312.3211810 f 312.321.1830

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