LTC1659CMS8-TRPBF Просмотр технического описания (PDF) - Linear Technology

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LTC1659CMS8-TRPBF

12-Bit Rail-to-Rail Micropower DAC in MSOP Package

Linear Technology 

LTC1659

OPERATION

Serial Interface

The data on the DIN input is loaded into the shift register

on the rising edge of the clock. The MSB is loaded first.

The DAC register loads the data from the shift register

when ⎯C⎯S/LD is pulled high. The CLK is disabled internally

when ⎯C⎯S/LD is high. Note: CLK must be low before ⎯C⎯S/LD

is pulled low to avoid an extra internal clock pulse.

The buffered output of the 12-bit shift register is available

on the DOUT pin which swings from GND to VCC. Multiple

LTC1659s may be daisy-chained together by connecting

the DOUT pin to the DIN pin of the next chip, while the CLK

and ⎯C⎯S/LD signals remain common to all chips in the

daisy chain. The serial data is clocked to all of the chips,

then the ⎯C⎯S/LD signal is pulled high to update all of them

simultaneously.

Voltage Output

The LTC1659’s rail-to-rail buffered output can source or

sink 5mA over the entire operating temperature range

while pulling to within 300mV of the positive supply

voltage or ground. The output swings to within a few

millivolts of either supply rail when unloaded and has an

equivalent output resistance of 40Ω when driving a load

to the rails. The output can drive 1000pF without going

into oscillation.

The output swings from 0V to the voltage at the REF pin,

i.e., there is a gain of 1 from the REF to VOUT. Please

note if REF is tied to VCC the output can only swing to

(VCC – VOS). See Applications Information.

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