ADV476KN50 Просмотр технического описания (PDF) - Analog Devices
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ADV476KN50 Datasheet PDF : 12 Pages
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ADV476–SPECIFICATIONS (VCC = +5 V ؎ 10%, IREF = 8.88 mA.
All Specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
All Versions Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution (Each DAC)
6
Bits
Accuracy (Each DAC)
Integral Nonlinearity
± 0.5
LSB max
Guaranteed Monotonic
Full Scale Error
Blank Level
±5
± 0.5
% max
LSB max
Full Scale = 2.15 ϫ IREF ϫ RL, IREF = 8.39 mA
BLANK = Logic Low
Offset Error
± 0.5
LSB max
BLANK = Logic High
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Current (RD Input Only)
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
2
0.8
± 10
± 100
7
2.4
0.4
± 50
7
V min
V max
µA max
µA max
pF typ
V min
V max
µA max
pF typ
VCC = 5.5 V, VIN = 0.4 V to VCC
VCC = 5.5 V, VIN = 0.4 V to VCC
ISOURCE = 500 µA, VCC = 4.5 V
ISINK = 5.0 mA, VCC = 4.5 V
VCC = 5.5 V, 0.4 V < VIN < VCC
ANALOG OUTPUTS
Max Output Voltage
1.5
Max Output Current
21
DAC to DAC Matching2
± 2.5
Analog Output Capacitance
10
V min
mA min
% max
pF typ
IO < 10 mA, IO = 2.15 ϫ IREF
VO ≤ 1 V
BLANK = Logic Low
CURRENT REFERENCE
Input Current (IREF) Range
Voltage at IREF
POWER SUPPLY
Supply Voltage, VCC
Supply Current, ICC
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Clock and Data Feedthrough3, 4
Glitch Impulse3, 4
–3/–10
VCC –3/VCC
mA min/mA max
V min/V max
IREF = 8.88 mA
4.5/5.5
220
6
V min/V max
mA max
%/V
fMAX = 66 MHz IO = 2.15 ϫ IREF, D0–D7 Unloaded
4.5 < VCC < 5.5 V, IO = 2.15 ϫ IREF, RL = 37.5 Ω,
CL = 30 pF, IREF = 8.88 mA.
–35
dB typ
75
pV secs typ
NOTES
1Temperature range (TMIN to TMAX); 0 to +70°C.
2Relative to the midpoint of the distribution of the three DACs measured at full scale.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load ≤10 pF, 37.5 Ω. D0–D7 output load ≤50 pF. See timing notes in Figure 2.
4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 k Ω resistor to
ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2 ϫ clock rate.
Specifications subject to change without notice.
–2–
REV. B
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