IDT77155L155PX Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

производитель

IDT77155L155PX

PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS

Integrated Device Technology 

IIDT77155

155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE

ADVANCED INFORMATION

Commercial Temperature Range

PIN DESCRIPTIONS (CONTINUED)

Symbol

RBYP

RCA/

RXEMPTY

RCLK

RCP

RD

RDAT0-

RDAT7

RFCLK

RFP

RGFC

RRCLK+

RRCLK-

RRDENB

Name

I/O

Receive Bypass I

Receive Cell

O

Available

Receive Clock O

Receive Cell

O

Read

I

Receive Data O

Receive FIFO I

Clock

Receive Frame O

Pulse

Receive Generic O

Flow Control

Receive Differential I

Reference Clock

Receive Read I

Enable

Description

Active high RBYP input disables clock recovery. If enabled, the receive different serial data

RXD+/- is sampled on the rising edged of the receive differential reference clock RRCLK+/-.

If RBYP is disabled, the receive clocks are recovered from RXD+/- bit stream. RBYP has an

integral pull down resistor.

Pin #: 41

This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the

tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the

polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is

tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy

protocol.

Pin #: 69

Provides a timing reference, and is a divide-by-8 version of tri-covered clock when RBYP is

disabled or RRCLK+/- when RBYP is enabled.

Pin #: 57

Receive GFC pulse indicates the start of the four generic flow control bits (GFC) in the

RGFC Pulse output. RCP is coincident with the most significant GFC bits. RCP is updated

on the rising edge of RCLK.

Pin #: 60

Active low read signal to read contents of addressed register. The data bus is driven by the

contents of the addresses register when the read signal is asserted along with the chip

select (CS) signal.

Pin #: 105

The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising

edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In

UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or

always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the

level-2 protocol.

Pin #: RDAT0/70, RDAT1/71, RDAT2/74, RDAT3/75, RDAT4/76, RDAT5/77, RDAT6/78,

RDAT7/79

The receive ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the

transmit data, and the transmit data parity signals are updated on the rising edge of this

clock. RRDENB is sampled on the rising edge of this clock.

Pin #: 67

An 8 KHz signal synchronized to RCLK. It is pulse high for one clock every 2430 RCLK

cycles for STS-3c or every 810 RCLK cycles for STS-1. It is updated on the rising edge of

RCLK.

Pin #: 58

Outputs the extracted generic flow control bits (GFC) in a serial stream. The four GFC bits

are output for each receive cell, and the first of the four bits is coincident with the RCP

output, RGFC is low until cell delineation is achieved. RGFC is updated on the rising edge of

RCLK.

Pin #: 59

Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock recovery

is enabled (RBYP = 0). When RBYP is enabled, RRCLK+/- is nominally a 155.52 MHz or

51.84 MHz 50% duty cycle clock and provides the timing for the internal receive functions.

RXD+/- is sampled on the rising edge of RRCLK+/-

Pin #: RRCLK+/34/ RRCLK-/33

Active low signal from ATM signifying that data will be sampled on RDAT[7:0] in the

following clock cycle. When sampled high, RSOC and RDAT[7:0] are tristated, if TSEN is

enabled. RRDENB must operate with RFCLK at high rate to prevent receive FIFO overflow

and loss of receive data.

Pin #: 68

8.03

5

Share Link: