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IDT77155L155PX

PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS

Integrated Device Technology 

IDT77155

155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE

PIN DESCRIPTIONS

ADVANCED INFORMATION

Commercial Temperature Range

Symbol

A0-A7

AGND

ALE

ALOS+

ALOS-

ATP1

ATP2

AVcc

CS

D1-D7

GND

INT

LF+

LF-

LFO

MPHYEN

RALM

RATE0

RATE1

Name

I/O

Address

I

Analog Ground G

Address Latch I

Enable

Analog Loss of I

Signal

Test pin

I

Test pin

I

Analog Power P

Chip Select

I

Data

I/O

Ground

G

Interrupt

O

Loop Filter

O

Special

O

Multi-phy Enable I

Receive Alarm O

Line Rate

I

Description

Address bus to select specific registers in the register set. The address pin A7 has an

integral pull-down resistor.

Pin #: A0/119, A1/120, A2/121, A3/122, A4/123, A5/124, A6/125, A7/126

These pins should be physically isolated from the other ground pins.

Pin #: 5, 7, 11, 29, 31, 35, 37

Latches the address bus when low, and is transparent when high. It allows interfacing to a

multiplexed address/data bus. ALE has an integral pull-up resistor.

Pin #: 127

Differential inputs indicate a loss of receive signal power. When ALOS+/- is asserted, data

on the RXD+/- inputs is squelched and the receive data/clock recovery PLL switches

to the reference clock. ALOS+/- has an effect only when RBYP is disabled. These inputs

must be dc-coupled.

Pin #: ALOS+ 28, ALOS- 27

Test pin for the transmit clock synthesis logic. When asserted, the TNB output of the clock

synthesis block is reflected on the LFO pin. ATP1 has an integral pull-down resistor.

Pin #: 40

Test pin for the receive clock/data recovery logic. When asserted, the CNB output of the clock

recovery block is reflected on the LF-pin. ATP2 has an integral pull-down resistor.

Pin #: 3

These power pins should be physically isolated from the other power pins and connected to a

well coupled 5v dc source.

Pin #: 4, 6, 8, 24, 30, 32, 36

Active low chip select to access registers.

Pin #: 100

Bidirectional data bus for register access during register reads and writes.

Pin #: D0/109, D1/110, D2/111, D3/112, D4/115, D5/116, D6/117, D7/118

Core, Ring and Thermal Grounds.

Pin #: 1, 19, 21, 38, 39, 56, 62, 64, 65, 72, 80, 102, 103, 106, 113, 128

Open drain interrupt signal which goes low when an interrupt source is active and unmasked

open from within the chip. This signal is cleared by appropriate reads to the interrupt

registers. INT is an open-drain output.

Pin #: 108

Special pin to output CAP voltage of the receive data/clock recovery logic when ATP2 is

enabled. Reference clock signal of the receive data/clock recovery logic.

Pin #: LF+/42, LF-/43

Special pin to output CAP voltage of the transmit clock synthesis logic when ATP1 is enabled.

Pin #: 44

When asserted, the multiphy enable signal converts the UTOPIA interface to be fully

compliant with the UTOPIA level-2 specification. In this mode, the TXADDR[1:0] and

RXADDR[1:0] bits determine the address of the device to be addressed. The default

operation of the chip is in single-phy UTOPIA level-1 mode. MPHYEN pin has an integral pull-

down resistor.

Pin #: 49

Output is asserted if line alarm indication signal (LAIS), path alarm indication signal (PAIS),

loss of signal (LOS), loss of frame (LOF), or loss of cell delineation (LOC) is detected in the

receive logic. RALM is updated on the rising edge of RCLK.

Pin #: 63

RATE inputs select the frame format and line rates for both the transmit and receive functions

RATE(1:0)

11

155.52 Mb/s, STS-3c / STM-1

10

51.84 Mb/s, STS-1

0X

Reserved

The RATE inputs have integral pull-up resistors, so the default is STS-3c

Pin #: RATE0/98, RATE1/97

8.03

4

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