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IDT77155L155PX

PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS

Integrated Device Technology 

IIDT77155

155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE

ADVANCED INFORMATION

Commercial Temperature Range

of any pattern other than “111” in bits 6-8 of K2 byte are

detected.

For SDH applications, Line AIS is declared when three

consecutive frames “111” pattern in bits 6-8 of K2 byte are

detected. Line AIS is removed when three consecutive

frames of any pattern other than “111” in bits 6-8 of K2 byte

are detected. The selection of SONET or SDH detection

criteria is set by control register.

The Line Remote Defect Indication (RDI) is detected in the

incoming data stream. Line RDI is declared when five con-

secutive frames of “110” pattern in bits 6-8 of K2 byte are

detected. Line RDI is removed when five consecutive frames

of any pattern other than “110” in bits 6-8 of K2 byte are

detected.

For SDH applications, Line RDI is declared when three

consecutive frames of “110” pattern in bits 6-8 of K2 byte are

detected. Line RDI is removed when three consecutive

frames of any pattern other than “110” in bits 6-8 of K2 byte

are detected. The selection of SONET or SDH detection

criteria is set by control register.

K1 and K2 bytes are extracted if new identical values are

received for 3 consecutive frames for Automatic Switch

Protection (APS) use.

The Line Far End Block Error (LFEBE) can be monitored

by extracting the 8-bit FEBE from the incoming third Z2 byte.

the error count range is from 0 to 24 errors. Any other value

is counted as zero error. Up to 192,000 (24x 8000) bit errors

can be detected for one second,

One 20-bit saturating counter is provided to accumulate

these FEBE errors. This counter is to be read and reset via

microprocessor interface.

The Pointer Interpreter interprets the incoming pointer

byte (H1, H2) to determine the location of the J1 byte (path

overhead) in the incoming STS-3c or STS-1 data stream.

The Pointer Interpreter detects loss of pointer (LOP) and

path AIS in the incoming STS-3c or STS-1 data stream.

LOP is declared when eight consecutive invalid pointers

or eight consecutive NDF enabled indications are detected.

LOP is removed when three consecutive same valid pointers

with normal NDF are detected.

Path AIS is declared when three consecutive “all-one”

pattern in H1 and H2 byte are detected. Path AIS is removed

when three consecutive same valid pointers with normal

NDF are detected or when a valid pointer with NDF enabled

is detected.

The B3 BER is monitored by the incoming Path BIP-8

error detection code (B3). The BIP-8 code is calculated over

all bits of the synchronous payload envelope after

descrambling by bit interleaved parity calculation using even

parity. And obtains errors by comparing the calculated BIP-

8 code with the BIP-8 code extracted from the B3 byte of the

next incoming frame. Up to 64,000 (8 x 8000) bit errors can be

detected for one second.

One 16-bit saturating counter is provided to accumulate

these BIP errors. This counter is to be read via microproces-

sor interface at least once per second for performance moni-

toring.

C2 Mismatch is detected in the incoming data stream. C2

Mismatch is declared when five consecutive frames of the

value other than “13h” in C2 byte are detected. C2 Mismatch

is removed when five consecutive frames of the value “13h”

in C2 byte are detected.

The Path Far End Block Error (PFEBE) can be monitored

by extracting the 4-bit FEBE from the incoming path status

byte (G1). the error count range is from “0000” to “1000” to

represent zero to eight errors. Any other value is counted as

zero error. Up to 64,000 (8 x 8000) bit errors can be detected

for one second,

One 16-bit saturating counter is provided to accumulate

these FEBE errors. This counter is to be read and reset via

microprocessor interface.

Path Remote Defect Indication (RDI-P) is detected by

checking the bit 5 of path status byte (G1) in the incoming data

stream. Path RDI is declared when ten consecutive frames of

value “1” in bit 5 of G1 byte are detected. Path RDI is removed

when ten consecutive frames of value “0” in bit 5 of G1 byte

are detected.

RECEIVE UTOPIA CELL FIFO

The Receive UTOPIA Cell FIFO provides functions for

ATM cell delineation, HEC error verification, cell filtering, and

ATM cell payload descrambling. This block also provides a

four cell deep receive FIFO.

Cell Delineation is for validating the HEC of a cell header

by checking with the CRC-8 calculation over first 4 bytes of

ATM cell header; the coset value of “55h” can be optionally

added to the HEC during validation. HEC validation uses the

state machine in CCITT recommendation I.432 and is shown

in Figure 1.

The state machine shown in Figure 1 is initialized to the

HUNT state in which every byte of ATM 53 byte is checked

for a valid HEC. Once correct HEC has been found, cell

delineation state machine enters the PRESYNC state that

validates HEC on a cell by cell basis. If additional DELTA

(value is suggested to be six) consecutive correct HECs are

validated, the state machine enters the SYNC state. How-

ever, if any incorrect HEC is found in the PRESYNC state, the

state machine reverts to HUNT state. Once in SYNC state, it

stays in the SYNC state until ALPHA (value is suggested to be

seven) consecutive incorrect HECs are detected. HUNT state

is entered and the search for a correct HEC on a byte by byte

basis resumes.

Cell could be discarded with HEC errors by using HEC

8.03

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