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IDT77155L155PX

PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS

Integrated Device Technology 

IDT77155

155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE

ADVANCED INFORMATION

Commercial Temperature Range

FUNCTIONAL DESCRIPTION

CLOCK RECOVERY

The clock recovery Block recovers the clock from the

receiving serial data stream. This block can be selected to

utilize reference clocks at 6.48 MHz or 19.44 MHz. This unit

provides a status bit to indicate whether it is locked to data or

the reference clock. The clock recovery unit also provides a

loss of signal (LOS) input and a diagnostic loopback.

The PLL originally locks to the reference clock. The PPL will

lock to the data when the frequency of the recovered clock is

within 244 ppm of the reference clock. Once in data lock, the

PLL switches to the reference clock if there is no data

transition for an 80 bit period or the recovered clock drifts for

over 244 ppm of the reference clock. The transmit clock could

be derived from the recovered clock (loop timing) by configu-

ration.

framing bytes (A1, A2) and the identity bytes (C1) are not

descrambled. The descrambling function can be disable by a

register control bit.

The B1 BER is monitored by the incoming section BIP-8

error detection code (B1). The BIP-8 code is calculated over

all bits of the complete STS-3c or STS-1 frame before

descrambling by bit interleaved parity calculation using even

parity. And obtains errors by comparing the calculated BIP-8

code with the BIP-8 code extracted from the B1 byte of the next

incoming frame. Up to 64,000 (8 x 8000) bit errors can be

detected for one second.

One 16-bit saturating counter is provided to accumulate

these BIP errors. This counter is to be read via microproces-

sor interface at least once per second for performance moni-

toring.

SERIAL TO PARALLEL

This block performs the serial to parallel conversion of

incoming bit serial data into byte serial data.

RECEIVE SONET FRAMER

The Receive SONET Framer performs frame synchroniza-

tion, descrambling, pointer interpretation, SONET section,

line, and path overhead processing, alarm and performance

monitoring functions.

The framer determines the out-of-frame/in-frame status for

the STS-3c/STS-1 data by checking the framing pattern (A1,

A2). Out-of-frame is declared when four consecutive frames

with errored framing patterns are received. While out-of-

frame, the framer searches for the correct framing pattern, in-

frame is declared upon detecting two consecutive error-free

framing patterns.

The Loss Of Frame (LOF) status is determined by monitor-

ing the out-of-frame/in-frame conditions. This block provides

the 3 ms out-of-frame timer and in-frame timer. The in-frame

timer accumulates when the out-of-frame is absent; it stops

accumulating and is reset to zero when the out-of-frame is

present. The out-of-frame timer accumulates when the out-of-

frame is present; it stops accumulating when the out-of-frame

is terminated. For the intermittent out-of-frame conditions, it is

only reset to zero when the out-of-frame is absent continu-

ously for 3 ms (i.e., the in-frame timer reaches 3 ms).

The LOF is declared when the accumulated out-of-frame

timer reaches 3 ms. Once detected, the LOF defect is termi-

nated when the in-frame timer reaches 3 ms.

The Loss Of Signal (LOS) Block checks the incoming

scrambled data availability. LOS is declared when 20 + 3 µs

of all-zero pattern is detected. Loss of signal is cleared when

two consecutive valid framing patterns is detected, and during

the intervening time (one frame), no all-zero pattern qualifying

as LOS defect exits.

The incoming data stream is descrambled. The scrambling

polynomial is 1 + x6 + X7 and the sequence length is 127. The

The B2 BER is monitored by the incoming Line BIP-8/24

error detection code (B2). The BIP-8/24 code is calculated

over all bits of the line overhead and synchronous payload

envelope after descrambling by bit interleaved parity calcula-

tion using even parity. And obtains errors by comparing the

calculated BIP-8/24 code with the BIP-8/24 code extracted

from the B2 byte of the next incoming frame. Up to 192,000 (24

x 8000) bit errors can be detected for one second. One 20-bit

saturating counter is provided to accumulate these BIP errors.

This counter is to be read via microprocessor interface at least

once per second for the performance monitoring. The defect

detection for B2 EBER is also provided.

The Receive B2 BER Detection Algorithm provides a

method for detection of a preset Bit Error Rate (BER) in the

incoming SONET/SDH data stream. Upon detection of the

preset level, the IDT77155 can optionally assert its interrupt

pin and provide status information. The algorithm provides

two identical, programmable BER detection blocks that will

allow the user to detect BER by setting two independent BER

thresholds. This can be used to provide the “warning” and

“fail” thresholds needed to comply with the SONET/SDH

specification for Automatic Protection Switching (APS).

To detect the BER for “warning” and “fail” level. Three

configuration registers are provided respectively.

Denominator (DM) register: 16-bit register, Number of

frames (frames = DM + 1) that are used to compute the BER.

Window Length (WL) register: 8-bit register, Length of the

sliding window in frames.

BIP Threshold (BT) register: 8-bit register, Value for the BIP

threshold.

The Denominator, Window Length, and BIP Threshold

registers are configured according to Table 1 for “warning” and

“fail” BER detection respectively. The first two rows are “fail”

levels, and the remaining are “warning” levels.

The Line Alarm Indication Signal (AIS) is detected in the

incoming data stream. Line AIS is declared when five con-

secutive frames “111” pattern in bits 6-8 of K2 byte are

detected. Line AIS is removed when five consecutive frames

8.03

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