NE564D Просмотр технического описания (PDF) - Philips Electronics

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NE564D

Phase-locked loop

Philips Electronics 

Philips Semiconductors

Phase-locked loop

Product specification

NE/SE564

6. If pulsed burst or ramp frequency is used for input signal, special

loop filter design may be required in place of simple single

capacitor filter on Pins 4 and 5. (See PLL application section)

7. The input signal to Pin 6 and the VCO feedback signal to Pin 3

must have a duty cycle of 50% for proper operation of the phase

detector. Due to the nature of a balanced mixer if signals are not

50% in duty cycle, DC offsets will occur in the loop which tend to

create an artificial or biased VCO.

8. For multiplier circuits where phase jitter is a problem, loop filter

capacitors may be increased to a value of 10 - 50µF on Pins 4,

5. Also, careful supply decoupling may be necessary. This

includes the counter chain VCC lines.

*NOTE:

Use R9-11 only if rise time is critical.

BIAS

ADJ

+5V

10k

2k

0.22µF 0.22µF

10k 1.2k

HYSTERESIS

ADJUST

2k

FSK

OUTPUT

FSK

INPUT

0.1µF

0.1µF 1k

1 10

2

6

7

1k

3

510Ω

+5V

9

*510Ω

11

300pF

4

5

300pF

15 16

NE564

14

10µF/8V

0–20pF

12

33pF

13

8

Figure 10. 10.8MHz FSK Decoder Using the 564

SR01034

1994 Aug 31

8

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