ML4824IS1 Просмотр технического описания (PDF) - Fairchild Semiconductor
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ML4824IS1 Datasheet PDF : 15 Pages
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ML4824
PRODUCT SPECIFICATION
Pin Configuration
ML4824
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
IEAO 1
16 VEAO
IAC 2
ISENSE 3
VRMS 4
SS 5
15 VFB
14 VREF
13 VCC
12 PFC OUT
VDC 6
RAMP 1 7
11 PWM OUT
10 GND
RAMP 2 8
9 DC ILIMIT
TOP VIEW
Pin Description
PIN
NAME
FUNCTION
1
IEAO
PFC transconductance current error amplifier output
2
IAC
PFC gain control reference input
3
ISENSE
Current sense input to the PFC current limit comparator
4
VRMS
Input for PFC RMS line voltage compensation
5
SS
Connection point for the PWM soft start capacitor
6
VDC
PWM voltage feedback input
7
RAMP 1
Oscillator timing node; timing set by RTCT
8
RAMP 2
When in current mode, this pin functions as as the current sense input; when in voltage
mode, it is the PWM input from PFC output (feed forward ramp).
9
DC ILIMIT PWM current limit comparator input
10 GND
Ground
11 PWM OUT PWM driver output
12 PFC OUT PFC driver output
13 VCC
Positive supply (connected to an internal shunt regulator)
14 VREF
Buffered output for the internal 7.5V reference
15 VFB
PFC transconductance voltage error amplifier input
16 VEAO
PFC transconductance voltage error amplifier output
2
REV. 1.0.6 11/7/03
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