ML4824IS1 Просмотр технического описания (PDF) - Fairchild Semiconductor

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ML4824IS1

Power Factor Correction and PWM Controller Combo

Fairchild Semiconductor 

PRODUCT SPECIFICATION

ML4824

In the case of leading edge modulation, the switch is turned

OFF right at the leading edge of the system clock. When the

modulating ramp reaches the level of the error amplifier

output voltage, the switch will be turned ON. The effective

duty-cycle of the leading edge modulation is determined

during the OFF time of the switch. Figure 5 shows a leading

edge control scheme.

One of the advantages of this control teccnique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to minimize

the momentary “no-load” period, thus lowering ripple

voltage generated by the switching action. With such

synchronized switching, the ripple voltage of the first stage

is reduced. Calculation and evaluation have shown that the

120Hz component of the PFC’s output ripple voltage can be

reduced by as much as 30% using this method.

L1

I1

+

VIN

DC

SW2 I2 I3

I4

SW1

RL

C1

REF +–EAU3

RAMP

OSC

CLK

U4

+

– U1

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

Figure 4. Typical Trailing Edge Control Scheme.

L1

I1

+

VIN

DC

SW2 I2 I3

I4

SW1

RL

C1

+–EAU3

REF

VEAO

RAMP

OSC

CLK

+ CMP

– U1

U4

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

Figure 5. Typical Leading Edge Control Scheme.

REV. 1.0.6 11/7/03

11

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