AD678KD Просмотр технического описания (PDF) - Analog Devices
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AD678KD Datasheet PDF : 14 Pages
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AD678
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a con-
version. CS should be LOW tSC before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
Before a conversion is started, End-of-Convert (EOC) is HIGH,
and the sample-hold is in track mode. After a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample. EOC goes HIGH when the con-
version is finished.
In track mode, the sample-hold will settle to ± 0.01% (12 bits)
in 1 µs maximum. The acquisition time does not affect the
throughput rate as the AD678 goes back into track mode more
than 1 µs before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
12-Bit Mode Coding Format (1 LSB = 2.44 mV)
Unipolar Coding
(Straight Binary)
Bipolar Coding
(Twos Complement)
VIN*
0V
5.000 V
9.9976 V
Output Code
000 . . . 0
100 . . . 0
111 . . . 1
VIN*
–5.000 V
–0.002 V
+0.000 V
+2.500 V
+4.9976 V
Output Code
100 . . . 0
111 . . . 1
000 . . . 0
010 . . . 0
011 . . . 1
*Code center.
OUTPUT ENABLE TRUTH TABLES
12-BIT MODE (12/8 = HIGH)
INPUTS
(CS U OE)
1
0
OUTPUT
DB11–DB0
High Z
Enable 12-Bit Output
8-BIT MODE (12/8 = LOW)
INPUTS
R/L HBE (CS U OE)
OUTPUTS
DB11 . . . DB4
XX 1
10
0
Unipolar 1 1
0
Mode
00
0
01
0
10
0
Bipolar 1 1
0
Mode
00
0
01
0
High Z
00 0 0 a bc d
ef ghi j kl
abc de f gh
i j kl 0000
aa a a a bc d
ef ghi j k1
abc de f gh
i j kl 0000
END-OF-CONVERT
In asynchronous mode, End-of-Convert (EOC) is an open drain
output (requiring a minimum 3 kΩ pull-up resistor) enabled by
End-of-Convert ENable (EOCEN). In synchronous mode,
EOC is a three-state output which is enabled by EOCEN and
CS. See the Conversion Status Truth Table for details. Access
(tBA) and float (tFD) timing specifications do not apply in asyn-
chronous mode where they are a function of the time constant
formed by the 10 pF output capacitance and the pull-up
resistor.
START CONVERSION TRUTH TABLE
INPUTS
SYNC CS SC STATUS
1
Synchronous 1
Mode
1
1
0
Asynchronous 0
Mode
0
1 X No Conversion
0
Start Conversion
0 Start Conversion
(Not Recommended)
0 0 Continuous Conversion
(Not Recommended)
X1
X
X0
No Conversion
Start Conversion
Continuous Conversion
(Not Recommended)
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
X = HIGH to LOW transition. Must stay low for t = tCP.
CONVERSION STATUS TRUTH TABLE
INPUTS
OUTPUT
SYNC CS EOCEN EOC
STATUS
1
1
Synchronous 1
Mode
1
00
00
1X
X1
0
1
High Z
High Z
Converting
Not Converting
Either
Either
0
Asynchronous 0
Mode* 0
X0
X0
X1
0
High Z
High Z
NOTES
l = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
*EOC requires a pull-up resistor in asynchronous mode.
Converting
Not Converting
Either
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
U = Logical OR.
a = MSB.
1 = LSB.
REV. C
–9–
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