MT88E39 Просмотр технического описания (PDF) - Mitel Networks

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MT88E39

Calling Number Identification Circuit

Mitel Networks 

MT88E39

Advance Information

C1 R1

IN+

IN-

C2 R4

R5

GS

R3

R2

VRef

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2

MT88E39

R1 = R4

R3 = (R2 x R5) / (R2 + R5)

For unity gain, R5 = R1

VOLTAGE GAIN

INPUT IMPEDANCE

(AVdiff) = R5/R1

(ZINdiff) = 2 R12 + (1/ωC)2

Figure 3 - Differential Input Configuration

IN+

C

RIN

IN-

RF

GS

VOLTAGE GAIN

(AV) = RF / RIN

VRef

MT88E39

Figure 4 - Single-Ended Input

Configuration

3-wire FSK Data Interface

The MT88E39 provides a powerful dual mode 3-wire

interface so that the 8-bit data words in the

demodulated FSK bit stream can be extracted

without the need either for an external UART or for

the microcontroller to perform the UART function in

software. The interface is specifically designed for

the 1200 baud rate and is comprised of the DATA,

DCLK (data clock) and DR (data ready) pins. Two

modes (0 and 1) are selectable via control of the

device’s MODE pin. In mode 0 the FSK bit stream is

output as demodulated. In mode 1 the FSK data byte

is store in a 1 byte buffer. Note that in mode 0 DR

and CD are open drain outputs; in mode 1 they are

CMOS outputs. DCLK is an output in mode 0, an

input in mode 1.

Mode 0

This mode is selected when the MODE pin is low. It

is the MT88E41 compatible mode where the FSK

data stream is output as demodulated. Since the

MODE pin was IC1 in MT88E41 and connected to

Vss, the MT88E39 will work in mode 0 when placed

in a MT88E41 socket.

In this mode, the MT88E39 receives the FSK signal,

demodulates it, and outputs the data directly to the

DATA pin (see Figure 11). For each received stop

and start bit sequence, the MT88E39 outputs a fixed

frequency clock string of 8 pulses at the DCLK pin.

Each DCLK rising edge occurs in the nominal centre

of a data bit. DCLK is not generated for the stop and

start bits. Consequently, DCLK will clock only valid

data into a peripheral device such as a serial to

parallel shift register or a microcontroller. The

MT88E39 also outputs an end of word pulse (Data

Ready) on the DR pin, which indicates the reception

of every 10-bit word (counting the start and stop bits)

sent from the end office. DR can be used to interrupt

a microcontroller or cause a serial to parallel

converter to parallel load its data into a

microcontroller. The mode 0 DATA pin can also be

connected to a personal computer’s serial

communication port after converting from CMOS to

RS-232 voltage levels.

Mode 1

This mode is selected when the MODE pin is high. In

this mode, the microcontroller supplies read pulses

at the DCLK pin (which is now an input) to shift the

8-bit data words out of the MT88E39, onto the DATA

pin. The MT88E39 asserts DR to denote the word

boundary and indicate to the microprocessor that a

new word has become available (see Figure 12).

Internal to the MT88E39, the demodulated data bits

are sampled and stored. The start and stop bits are

stripped off. After the 8th bit, the data byte is parallel

loaded into an 8 bit shift register and DR goes low.

The shift register’s contents are shifted out to the

DATA pin on the supplied DCLK’s rising edge in the

order they were received.

If DCLK begins while DR is low, DR will return to high

upon the first DCLK. This feature allows the

associated interrupt to be cleared by the first read

pulse. Otherwise DR is low for half a nominal bit time

(1/2400 sec). After the last bit has been read,

additional DCLKs are ignored.

Note that in both modes, the 3-pin interface may also

output data generated by speech or other voiceband

5-4

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