T8110-BAL-DB Просмотр технического описания (PDF) - Agere -> LSI Corporation
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T8110-BAL-DB
Agere -> LSI Corporation
T8110-BAL-DB Datasheet PDF : 222 Pages
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Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
Data Sheet
May 2001
Contents
Table of Contents (continued)
Page
14.2.1 Memory Architecture and Configuration ........................................................................................146
14.2.1.1 Connection Memory .......................................................................................................... 146
14.2.1.1.1 Virtual Channel Switching, Nonbonded Connections .................................. 147
14.2.1.1.2 Virtual Channel Switching, Bonded Connections ........................................ 147
14.2.1.2 Data Memory ..................................................................................................................... 148
14.2.1.3 Virtual Channel Memory .................................................................................................... 149
14.2.2 Standard Switching ........................................................................................................................ 149
14.2.2.1 Constant Delay and Minimum Delay Connections ............................................................ 149
14.2.2.2 Pattern Mode ..................................................................................................................... 149
14.2.2.3 Subrate .............................................................................................................................. 149
14.2.2.3.1 Subrate Switching Overview ........................................................................ 150
14.2.2.3.2 Subrate Switching Using T8110 .................................................................. 151
14.2.2.3.3 Subrate Packing of Outgoing Bytes ............................................................. 152
14.2.2.3.4 Subrate Unpacking of Incoming Bytes ........................................................ 153
14.2.3 Virtual Channel (Packet Payload) Switching ................................................................................. 155
14.2.3.1 Nonbonded Channels ........................................................................................................ 155
14.2.3.2 Subrate .............................................................................................................................. 157
14.2.3.3 Bonded Channels .............................................................................................................. 158
14.2.3.4 External Buffer Access ......................................................................................................160
14.2.3.4.1 Overview ......................................................................................................160
14.2.3.4.2 Descriptor Table ..........................................................................................161
14.2.3.4.3 External Buffer ............................................................................................. 162
14.2.3.4.4 Transfer Protocol ......................................................................................... 162
14.2.3.4.5 External Buffer Data Transfer ...................................................................... 164
14.2.3.4.6 Descriptor Table Update .............................................................................. 164
14.2.3.5 T8110 Packet Switching, Circuit Operation .......................................................................164
14.2.3.5.1 System Errors Due to Packet Switching ...................................................... 165
15 Electrical Characteristics ................................................................................................................................. 166
15.1 Absolute Maximum Ratings ................................................................................................................... 166
15.1.1 Handling Precautions ..................................................................................................................... 166
15.2 Crystal Specifications ............................................................................................................................ 166
15.2.1 XTAL1 Crystal ................................................................................................................................166
15.2.2 XTAL2 Crystal ................................................................................................................................167
15.2.3 Reset Pulse ................................................................................................................................... 168
15.3 Thermal Considerations for the 272 PBGA ........................................................................................... 168
15.4 dc Electrical Characteristics ..................................................................................................................168
15.4.1 PCI Signals .................................................................................................................................... 168
15.4.2 Electrical Drive Specifications, CT_C8 and /CT_FRAME .............................................................. 168
15.4.3 All Other Pins ................................................................................................................................. 169
15.5 H-Bus Timing ......................................................................................................................................... 169
15.5.1 Timing Diagrams ............................................................................................................................ 169
15.6 ac Electrical Characteristics ..................................................................................................................170
15.6.1 Skew Timing, H-Bus ...................................................................................................................... 170
15.7 Hot-Swap ............................................................................................................................................... 171
15.7.1 LPUE (Local Pull-Up Enable) ........................................................................................................ 171
15.8 Decoupling ............................................................................................................................................171
15.9 APLL VDD Filter ...................................................................................................................................... 171
15.10 PC Board PBGA Considerations ........................................................................................................... 172
15.11 Unused Pins .......................................................................................................................................... 172
6
Agere Systems Inc.
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