T8110-BAL-DB Просмотр технического описания (PDF) - Agere -> LSI Corporation
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T8110-BAL-DB
Agere -> LSI Corporation
T8110-BAL-DB Datasheet PDF : 222 Pages
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Data Sheet
May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
Contents
Table of Contents (continued)
Page
12 Error Reporting and Interrupt Control .............................................................................................................. 113
12.1 Interrupt Control Registers .................................................................................................................... 113
12.1.1 Interrupts Via External FG[7:0] Registers ...................................................................................... 113
12.1.1.1 FGIO Interrupt Pending Register ....................................................................................... 113
12.1.2 Interrupts Via External GP[7:0] ...................................................................................................... 115
12.1.2.1 GPIO Interrupt Pending Register ....................................................................................... 115
12.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ................................................................ 116
12.1.3 Interrupts Via Internal System Errors ............................................................................................. 116
12.1.4 System Interrupt Pending High/Low Registers .............................................................................. 117
12.1.5 System Interrupt Enable High/Low Registers ................................................................................ 118
12.1.6 Interrupts Via Internal Clock Errors ................................................................................................119
12.1.7 Clock Interrupt Pending High/Low Registers ................................................................................. 120
12.1.8 Clock Interrupt Enable High/Low Registers ................................................................................... 121
12.1.9 Interrupt Servicing Registers .......................................................................................................... 122
12.1.9.1 Arbitration Control Register ............................................................................................... 122
12.1.10 PCI_INTA Output Select Register .................................................................................................. 122
12.1.10.1 SYSERR and CLKERR Output Select Register ................................................................ 122
12.1.10.2 Interrupt In-Service Registers ........................................................................................... 123
12.2 Error Reporting and Interrupt Controller Circuit Operation .................................................................... 125
12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] ....................................................................... 126
12.2.2 Internally Sourced System Error Interrupts ....................................................................................126
12.2.3 Internally Sourced Clock Error Interrupts ....................................................................................... 126
12.2.4 Arbitration of Pending Interrupts .................................................................................................... 126
12.2.4.1 Arbitration Off .................................................................................................................... 126
12.2.4.2 Flat Arbitration ...................................................................................................................126
12.2.4.3 Tier Arbitration ...................................................................................................................126
12.2.4.3.1 Pre-Empting Disabled ..................................................................................127
12.2.4.3.2 Pre-Empting Enabled ..................................................................................127
12.2.5 CLKERR Output ............................................................................................................................. 127
12.2.6 SYSERR Output ............................................................................................................................ 127
12.2.7 PCI_INTA# Output ......................................................................................................................... 127
12.2.8 System Handling of Interrupts ........................................................................................................ 127
13 Test and Diagnostics ....................................................................................................................................... 128
13.1 Diagnostics Control Registers ............................................................................................................... 128
13.1.1 FG Testpoint Enable Register ........................................................................................................ 128
13.1.2 GP Testpoint Enable Register .......................................................................................................129
13.1.3 State Counter Modes Registers .....................................................................................................132
13.1.4 Miscellaneous Diagnostics Low Register ....................................................................................... 133
13.1.5 External Buffer Retry Timer Register ............................................................................................. 134
13.2 Diagnostic Circuit Operation .................................................................................................................. 135
14 Connection Control—Standard and Virtual Channel ............................................................................... ....... 136
14.1 Programming Interface ..........................................................................................................................136
14.1.1 PCI Interface .................................................................................................................................. 136
14.1.1.1 PCI Connection Memory Programming .............................................................................136
14.1.1.2 PCI Virtual Channel Memory Programming ......................................................................138
14.1.2 Microprocessor Interface ............................................................................................................... 139
14.1.2.1 Microprocessor Connection Memory Programming ..........................................................139
14.1.2.2 Microprocessor Virtual Channel Memory Programming ............................................... 144
14.2 Switching Operation .............................................................................................................................. 146
Agere Systems Inc.
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