T8110-BAL-DB Просмотр технического описания (PDF) - Agere -> LSI Corporation

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T8110-BAL-DB

Ambassador® T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine

Agere -> LSI Corporation 

Ambassador T8110 PCI-Based H.100/H.110 Switch

and Packet Payload Engine

Data Sheet

May 2001

Contents

Table of Contents

Page

1 Introduction ............................................................................................................................................................1

1.1 Features .......................................................................................................................................................... 1

2 Pin Description ...................................................................................................................................................... 8

2.1 Interface Signals ............................................................................................................................................. 8

2.2 T8110 Pinout Information ............................................................................................................................. 11

2.3 Special Buffer Requirements ........................................................................................................................ 18

2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down ................................................................................... 18

2.3.2 Local Bus Signal Internal Pull-Up .................................................................................................... 18

3 Main Architectural Features ................................................................................................................................ 19

3.1 T8110 Architecture .......................................................................................................................................19

4 PCI Interface ....................................................................................................................................................... 22

4.1 Target ........................................................................................................................................................... 22

4.1.1 PCI Interface Registers ....................................................................................................................23

4.1.2 Register Space Target Access ........................................................................................................29

4.1.3 Connection Memory Space Target Access .....................................................................................29

4.1.4 Data Memory Space Target Access ................................................................................................ 29

4.1.4.1 Posted Write Transaction .................................................................................................... 29

4.1.4.2 Delayed Read Transaction .................................................................................................. 30

4.1.5 Virtual Channel Memory Space Target Access ............................................................................... 30

4.1.5.1 Posted Write Transaction .................................................................................................... 30

4.1.5.2 Delayed Read Transaction .................................................................................................. 30

4.1.6 Minibridge Space Target Access ..................................................................................................... 30

4.1.6.1 Posted Write Transaction .................................................................................................... 31

4.1.6.2 Delayed Read Transaction .................................................................................................. 31

4.2 Initiator ..........................................................................................................................................................31

4.2.1 PUSH Operation (Upstream Transaction) ....................................................................................... 31

4.2.2 PULL Operation (Downstream Transaction) .................................................................................... 32

4.3 Configuration Space/EEPROM Interface ...................................................................................................... 34

4.3.1 Loadable PCI Configuration Space Via EEPROM ........................................................................... 36

5 Microprocessor Interface ..................................................................................................................................... 38

5.1 Intel/Motorola Protocol Selector ....................................................................................................................38

5.2 Word/Byte Addressing Selector ....................................................................................................................38

5.3 Access Via the Microprocessor Bus ............................................................................................................. 39

5.3.1 Microprocessor Interface Register Map ........................................................................................... 40

5.3.2 Register Space Access ....................................................................................................................44

5.3.3 Connection Memory Space Access .................................................................................................44

5.3.4 Data Memory Space Access ........................................................................................................... 45

5.3.5 Virtual Channel Memory Space Access ..........................................................................................45

6 Operating Control and Status .............................................................................................................................. 46

6.1 Control Registers .......................................................................................................................................... 46

6.1.1 Reset Registers ............................................................................................................................... 46

6.1.2 Master Output Enable Register ....................................................................................................... 47

6.1.3 Connection Control—Virtual Channel Enable and Data Memory Selector Register ........................ 48

6.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register ..................................... 49

6.1.5 Phase Alignment Select Register .................................................................................................... 50

6.1.6 Fallback Control Register ................................................................................................................ 50

6.1.7 Fallback Type Select Register ......................................................................................................... 51

6.1.8 Fallback Trigger Registers ...............................................................................................................51

6.1.9 Watchdog Select, C8, and NETREF Registers ................................................................................ 52

2

Agere Systems Inc.

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