W83629D Просмотр технического описания (PDF) - Winbond

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W83629D

PCI TO ISA BRIDGE SET

Winbond 

W83628F & W83629D

8.9 WISA_STS-ISA BRIDGE ERROR STATUS REGISTER

Address Offset:

42h

Default Value:

00h

Attribute:

Read/Write

Bit 7:3

Reserved.

Bit 2

IOCHK# Pin State.

This bit reflects the inverse state of IOCHK# pin on the ISA bus.

Bit 1

Reserved.

Bit 0

Byte Lane Error.

This bit is set if the ISA bridge detects an illegal byte lane combination for a

PCI I/O cycles.

8.10 WISA_FADC-ISA BRIDGE FAST DECODERS CONTROL REGISTER

Address Offset:

50h

Default Value:

00h

Attribute:

Read/Write

Bit 7

Enable/Disable Fast I/O Address Decoder # 7.

Bit 6

Enable/Disable Fast I/O Address Decoder # 6.

Bit 5

Enable/Disable Fast I/O Address Decoder # 5.

Bit 4

Enable/Disable Fast I/O Address Decoder # 4.

Bit 3

Enable/Disable Fast I/O Address Decoder # 3.

Bit 2

Enable/Disable Fast I/O Address Decoder # 2.

Bit 1

Enable/Disable Fast I/O Address Decoder # 1.

Bit 0

Enable/Disable Fast I/O Address Decoder # 0.

8.11 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 0 MASK CONTROL REGISTER

Address Offset:

58h

Default Value:

00h

Attribute:

Read/Write

This register is used to mask address bits(A7~A0) for fast address decoder # 0, if the corresponding

bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address

decoder # 0.

8.12 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 1 MASK CONTROL REGISTER

Address Offset:

59h

Default Value:

00h

Attribute:

Read/Write

This register is used to mask address bits(A7~A0) for fast address decoder # 1, if the corresponding

bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address

decoder # 1.

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