UCB1500 Просмотр технического описания (PDF) - Philips Electronics
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UCB1500 Datasheet PDF : 58 Pages
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Table 4: Function 0 configuration registers…continued
31-24
23-16
15-8
7-0
Subsystem ID Write = 3400
Subsystem Vendor ID Write = 1131
Reserved
PMC =
Next Item Per = 00
Capability ID = 01
4801 (VAUX_AV = 0, no autoload)
C801 (VAUX_AV = 1, no autoload)
Modified by BIOS via writing to 6Ah, or EEPROM
autoloading to PCI-PM1.1
Reserved
PMCSR = 0000 (S)
Address
6Ch
70-7Fh
80h
84h
[01-00]: Vendor ID (read only): Programmable through EEPROM interface, or
register 40h. Default value = 1131h
[03-02]: Device ID (read only): Programmable through EEPROM interface, or
register 42h. Default value = 3400h
[05-04]: Command Register
Table 5:
Bit
15-10
9(r)
8
7(r)
6
5(r)
4(r)
3(r)
2
1(r)
0
Command Register bit description
Description
Reserved.
Fast Back-to-back Transactions
Always 0, fast back-to-back transactions is not supported.
SERR enable
If set, SERR driver is enabled; if 0, SERR is disabled.
Address/Data Stepping
Always 0, address/data stepping is not implemented.
Parity Error Response
When set, the device must take its normal action when a parity error is detected.
If this bit is 0, the device must ignore any parity errors that it detects and continue
normal operation.
VGA Snooping
Always 0, not implemented.
Memory Write and Invalidate Command
Always 0, UCB1500 does not generate memory write and invalidate command.
Special Cycle Response
Always 0, UCB1500 ignores all special cycles.
Bus Master Control
PCI Master access enable; this bit must be enabled to activate UCB1500 DMA
register.
1 = enable.
Memory Space Response
Always 0, UCB1500 does not respond to memory space accesses.
I/O Space Control
UCB1500 control register I/O space access enable.
1 = enable.
9397 750 06854
Objective specification
Rev. 01 — 4 February 2000
© Philips Electronics N.V. 2000. All rights reserved.
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