SP8854E Просмотр технического описания (PDF) - Mitel Networks

Номер в каталоге

Компоненты Описание

производитель

SP8854E

0.3-6.0V; 2-7GHz synthesiser. For complete 2-7GHz single chip system

Mitel Networks 

SP8854E

Pin

Description

1-11, 42-44

These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these

pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in

buffers when pin 39 is low.

13 (RF INPUT)

14 (RF INPUT)

Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into

pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC

biased.

17 (LOCK DETECT INPUT)

A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give

an external indication of phase lock.

18 (C-LOCK DETECT)

A capacitor connected to this point determines the lock detect integrator time constant and can

be used to vary the sensitivity of the phase lock indicator.

19 (RSET)

20 (CHARGE PUMP OUTPUT)

An external resistor from pin 19 to VCC sets the charge pump output current.

The phase detector output is a single ended charge pump sourcing or sinking current to the

inverting input of an external loop filter.

21 (CHARGE PUMP REF)

Connected to the non-inverting input of the loop filter to set the optimum DC bias.

22 (FREF/ FPD ENABLE)

Part of the input bus. When this pin is high, the FREF/ FPD outputs are enabled.

High is open circuit.

23 (CONTROL DIRECTION)

This pin controls charge pump output direction. When pin 23 is high, the output sinks current

when FPD > FREF or when the RF phase leads the reference phase. When pin 23 is low, the

relationship is reversed (see Table 3).

24 FPD if pin 23 is high

FREF if pin 23 is low

25 FPD if pin 23 is low

FREF if pin 23 is high

27 (Ref. oscillator capacitor)

RF divider output pulses. FPD = RF input frequency/(M.N1A). Pulse width = 8 RF input cycles

(1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. FREF = reference input frequency/R. Pulse width = high period

of Ref input.

Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as

an onboard crystal oscillator.

28 (REF IN/XTAL)

This pin is the input buffer amplifier for an external reference signal. This amplifier provides the

active element if an onboard crystal oscillator is used.

29-38

These pins set the reference divider ratio R. High is open circuit.

39 (STROBE)

When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump

output is disabled. When pin 39 is low the data on the RF data and PD gain pins is fixed in the

buffers, the buffers are loaded into the RF counters and the PD gain control, all the counters are

active, and the charge pump is enabled. High is open circuit.

40, 41 (PD gain)

These pins set the charhe pump current multiplication factor (see Table 2). The data is

transparent into the buffers when pin 39 is high and frozen when pin 39 is low.

High is open circuit.

Table 1 Pin descriptions

3

Share Link: