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ORT82G5

ORCA® ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC

Agere -> LSI Corporation 

ORCA ORT82G5 FPSC Eight-Channel

1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface

Preliminary Data Sheet

July 2001

Programmable Features (continued)

s Built-in testability:

— Full boundary scan (IEEE 1149.1 and Draft

1149.2 JTAG).

— Programming and readback through boundary

scan port compliant to IEEE Draft 1532:D1.7.

— TS_ALL testability function to 3-state all I/O pins.

— New temperature-sensing diode.

s Improved built-in clock management with program-

mable phase-locked loops (PPLLs) provide optimum

clock modification and conditioning for phase, fre-

quency, and duty cycle from 20 MHz up to 420 MHz.

s New cycle stealing capability allows a typical 15% to

40% internal speed improvement after final place

and route. This feature also enables compliance with

many setup/hold and clock to out I/O specifications

and may provide reduced ground bounce for output

buses by allowing flexible delays of switching output

buffers.

Programmable Logic System Features

s PCI local bus compliant for FPGA I/Os.

s Improved PowerPC ®860 and PowerPC II high-

speed synchronous microprocessor interface can be

used for configuration, readback, device control, and

device status, as well as for a general-purpose inter-

face to the FPGA logic, RAMs, and embedded stan-

dard cell blocks. Glueless interface to synchronous

PowerPC processors with user-configurable address

space provided.

s New embedded AMBA ™ specification 2.0 AHB sys-

tem bus (ARM ® processor) facilitates communica-

tion among the microprocessor interface,

configuration logic, embedded block RAM, FPGA

logic, and embedded standard cell blocks.

s New network PLLs meet ITU-T G.811 specifications

and provide clock conditioning for DS-1/E-1 and

STS-3/STM-1 applications.

s Flexible general purpose PPLLs offer clock multiply

(up to 8x), divide (down to 1/8x), phase shift, delay

compensation, and duty cycle adjustment combined.

s Variable size bused readback of configuration data

capability with the built-in microprocessor interface

and system bus.

s Internal, 3-state, and bidirectional buses with simple

control provided by the SLIC.

s New clock routing structures for global and local

clocking significantly increases speed and reduces

skew (<200 ps for OR4E4).

s New local clock routing structures allow creation of

localized clock trees.

s New double-data rate (DDR) and zero-bus turn-

around (ZBT) memory interfaces support the latest

high-speed memory interfaces.

s New 2x/4x uplink and downlink I/O capabilities inter-

face high-speed external I/Os to reduced speed

internal logic.

s ORCA Foundry 2000 development system software.

Supported by industry-standard CAE tools for design

entry, synthesis, simulation, and timing analysis.

s Meets universal test and operations PHY interface

for ATM (UTOPIA) Levels 1, 2, and 3; as well as

POS-PHY3. Also meets proposed specifications for

UTOPIA Level 4 and POS-PHY3 (2.5 Gbits/s) and

POS-PHY4 (10 Gbits/s) interface standards for

packet-over-SONET as defined by the Saturn Group.

s Two new edge clock routing structures allow up to

seven high-speed clocks on each edge of the device

for improved setup/hold and clock to out perfor-

mance.

6

Agere Systems Inc.

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