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L9823(2003) Просмотр технического описания (PDF) - STMicroelectronics

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L9823 Datasheet PDF : 12 Pages
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L9823
APPLICATIONS INFORMATION
The typical application diagram for parallel Input SPI control is shown in Figure 4.
Figure 4. Typical Application Circuit Diagram for the L9823 Circuit.
VDD
VOLTAGE
REGULATOR
VBAT
µP
SFPD
15
CSB
10
SCLK
3
SI
4
SO
9
Reset
22
16 VDD
OL0
Reset
Undervoltage
RESET
Q0
Q0
Q1
Q2 ISCB0
Q3
Q4
Q5 OT0
Q6
Q7 Diag0
Diag0
Diag1 Q1
Diag2
Diag3
Diag4
Diag1
Q2
Diag2
Diag5 Q3
Diag6 Diag3
Diag7 Q4
Diag4
Q5
Diag5
Q6
Reset Diag6
Q7
Diag7
Gate
Control
Over
Temperature
Detect
GND 5 -8
17 - 20
-
+
VDG
=
+
-
-
+
=
OUT0
24
IOL
CH0
CH1
CH2
CH3
CH4
CH5
CH7
CH7
U459
OUT1
23
OUT2
14
OUT3
13
OUT4
12
OUT5
11
OUT6
2
OUT7
1
R, L loads
U459
For higher current driving capability more outputs of the same kind can be paralleled. In this case the maximum
flyback energy should not exceed the limit value for single output.
The immunity of the circuit with respect to the transients at the output is verified during the characterization for
Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with
200pF series capacitor. The correct function of the circuit with the Test Pulses coupled to the outputs is verified
during the characterization for the typical application with R = 16to 200, L= 0 to 600mH loads. All outputs
withstand testpulses without damage.
10/12

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