MT89L86AP Просмотр технического описания (PDF) - Mitel Networks
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MT89L86AP Datasheet PDF : 40 Pages
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MT89L86
Advance Information
STi3
STi4
STi5
STi6/A6
STi7/A7
VDD
FR
CLK
STi8/A0
STi9/A1
STi10/A2
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
STo3
STo4
STo5
STo6/A6
STo7/A7
VSS
AD0
AD1
AD2
AD3
AD4
44 PIN PLCC
VSS
1
DTA 2
STi0 3
STi1 4
STi2 5
AS/ALE 6
STi3 7
STi4 8
STi5 9
STi6/A6 10
STi7/A7 11
VDD 12
RESET 13
FR 14
CLK 15
STi8/A0 16
STi9/A1 17
STi10/A2 18
IM 19
STi11/A3 20
STi12/A4 21
STi13/A5 22
DS/RD 23
R/W\WR 24
48 CSTo
47 ODE
46 STo0
45 STo1
44 STo2
43 STi14/STo8
42 STo3
41 STo4
40 STo5
39 STo6/A6
38 STo7/A7
37 VSS
36 VDD
35 AD0
34 AD1
33 AD2
32 AD3
31 AD4
30 STi15/STo9
29 AD5
28 AD6
27 AD7
26 CS
25 VSS
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Pin Description
Figure 2 - Pin Connections
Pin #
44 48
PLCC SSOP
Name
Description
2
2
DTA Data Acknowledgment (Open Drain Output). This active low output indicates that a
data bus transfer is complete. A pull-up resistor is required at this output.
3-5 3-5
7-9 7-9
STi0-5 ST-BUS Inputs 0 to 5 (5V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels,
respectively.
10 10 STi6/A6 ST-BUS Input 6/Addr.6 input (5V-tolerant Input). The function of this pin is determined
by the switching configuration enabled. If non-multiplexed CPU bus is used along with
a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function.
For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus
interface is selected, this pin assumes STi6 function. See Control Register bits
description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 and STi6 inputs are required simultaneously
(e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate conversion between 2.048Mb/
s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6.
11 11 STi7/A7 ST-BUS Input 7/Addr.7 input (5V-tolerant Input): The function of this pin is determined
by the switching configuration enabled. If non-multiplexed CPU bus is used along with
a higher input rate of 8.192 Mb/s, this pin provides A7 address input function.
For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus is
selected, this pin assumes STi7 function. See Control Register bits description and
Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A7 and STi7 inputs are required simultaneously
(e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin
STo7/A7.
2
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