AD9832(RevA) Просмотр технического описания (PDF) - Analog Devices
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AD9832 Datasheet PDF : 16 Pages
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AD9832
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale, a point 0.5 LSB be-
low the first code transition (000 . . . 00 to 000 . . . 01) and full
scale, a point 0.5 LSB above the last code transition (111 . . . 10
to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is depen-
dent on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical Signal to (Noise + Distortion) ratio for a sine wave
input is given by
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms
sum of harmonics to the rms value of the fundamental. For
the AD9832, THD is defined as:
THD = 20 log
V
2
2
+
V
2
3
+
V
2
4
+
V
2
5
+
V
2
6
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica-
tions. When voltages greater than those specified for the output
compliance are generated, the AD9832 may not meet the speci-
fications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the fundamental
frequency and images of the MCLK frequency are present at the
output of a DDS device. The spurious free dynamic range (SFDR)
refers to the largest spur or harmonic present in the band of
interest. The wide band SFDR gives the magnitude of the larg-
est harmonic or spur relative to the magnitude of the fundamental
frequency in the bandwidth ±2 MHz about the fundamental fre-
quency. The narrow band SFDR gives the attenuation of the
largest spur or harmonic in a bandwidth of ± 50 kHz about the
fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the MCLK
signal relative to the fundamental frequency in the AD9832’s out-
put spectrum.
Table I. Control Registers
Register
Size
FREQ0 REG 32 Bits
FREQ1 REG 32 Bits
PHASE0 REG 12 Bits
PHASE1 REG 12 Bits
PHASE2 REG 12 Bits
PHASE3 REG 12 Bits
Description
Frequency Register 0. This de-
fines the output frequency, when
FSELECT = 0, as a fraction of
the MCLK frequency.
Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of
the MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added to
the output of the phase accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the con-
tents of this register are added to
the output of the phase accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
Table II. Addressing the Registers
A3 A2
A1
A0
Destination Register
0
0
0
0
FREQ0 REG 8 L LSBs
0
0
0
1
FREQ0 REG 8 H LSBs
0
0
1
0
FREQ0 REG 8 L MSBs
0
0
1
1
FREQ0 REG 8 H MSBs
0
1
0
0
FREQ1 REG 8 L LSBs
0
1
0
1
FREQ1 REG 8 H LSBs
0
1
1
0
FREQ1 REG 8 L MSBs
0
1
1
1
FREQ1 REG 8 H MSBs
1
0
0
0
PHASE0 REG 8 LSBs
1
0
0
1
PHASE0 REG 8 MSBs
1
0
1
0
PHASE1 REG 8 LSBs
1
0
1
1
PHASE1 REG 8 MSBs
1
1
0
0
PHASE2 REG 8 LSBs
1
1
0
1
PHASE2 REG 8 MSBs
1
1
1
0
PHASE3 REG 8 LSBs
1
1
1
1
PHASE3 REG 8 MSBs
Table III. 32-Bit Frequency Word
16 MSBs
16 LSBs
8 H MSBs 8 L MSBs 8 H LSBs 8 L LSBs
Table IV. 12-Bit Frequency Word
4 MSBs (The 4 MSBs of the
8-Bit Word Loaded = 0)
8 LSBs
–8–
REV. A
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