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SPT2110SCT

NTSC/PAL VIDEO DECODER

Signal Processing Technologies 

The SPT2110 is part of a three-chip solution for high quality

video signal decoding. The companion integrated circuits are

the SPT9210, a dual analog video processor, and the

SPT7852, dual 10-bit ADC. The SPT9210 provides internal

DC restoration and Automatic Gain Control (AGC) of the

video signal. The SPT7852 provides 10-bit resolution video

digitization.

The SPT2110 operates from a single +3.3 V supply. It is

available in a 100-lead PQFP package and operates over the

commercial temperature range.

GENERAL OVERVIEW

The SPT2110 video decoder is compatible with NTSC or PAL

video standards. It has two 9-bit digitized video inputs busses

and three 8-bit video data output busses with sync, blank,

field indicator and chrominance data indicator output signals.

The SPT2110 is fully programmable through the command

registers. Each command register is accessed by a single

address register. The control lines and the bidirectional 8-bit

data bus provide access to the command and address

registers.

DIGITAL VIDEO INPUT DATA BUSSES

The two 9-bit digital video input data busses have 3.3 volt

compatible logic levels. In composite mode, the composite

digital video is input through the LUM8…0, 9-bit data bus. In

component mode, the luminance component is input through

the LUM8…0, 9-bit data bus while the chrominance compo-

nent is input through the CHR8…0, 9-bit data bus. Register 1

selects whether composite or component video input data will

be processed. The input busses expect valid data on each

rising edge of the clock input. Refer to the timing diagram,

figure 1.

Table I - Digital Image Input Busses Description

Bus Label

LUM8...0

CHR8...0

Description

Digitized video data for composite

video or the luminance signal input.

LUM8 is the MSB, and LUM0 is the LSB.

Digitized video data for the chromi-

nance signal input. CHR8 is the MSB,

and CHR0 is the LSB.

DECODED DIGITAL VIDEO OUTPUT DATA

BUSSES

The three 8-bit digital video output data busses on the

SPT2110 have 3.3 volt compatible logic levels. All three

busses are used for RGB digital video data output. Two

busses are used for YC (YCrCb) digital video data. The RGB

data is NTSC or PAL video that has been translated to RGB

(4:4:4) format. The YC data is NTSC or PAL video that has

been translated to YCrCb (4:2:2) format. The luminance

portion of the YCrCb output (Y) is output on the Y/R7…0 bus,

and the color difference signal data (Cr and Cb) is output on

the C/B7…0 bus. Cr and Cb are alternately output every other

clock cycle. All three busses may be programmed to a tri-

state level. Refer to the timing diagram, figure 1.

Table II - Digital Video Output Busses Description

Bus Label

Y/R7...0

C/G7...0

B7...0

Description

Decoded video data for Y (luminance) or R

(red). Y/R7 is the MSB, and Y/R0 is the

LSB.

Decoded video data for C (chrominance)

or G (green). C/G7 is the MSB, and C/G0

is the LSB.

Decoded video data for B (blue). B7 is

the MSB, and B0 is the LSB.

VIDEO TIMING OUTPUT SIGNALS

The video timing output signals have 3.3 volt compatible logic

levels. They produce the temporal information that identifies

the spacial position of the video signal. They are used

downstream to synchronize signals and for odd/even field

identification. These discrete output timing control signals

may be programmed as positive or negative true logic or they

may be tri-stated.

The video timing output signals are described in table III. The

signal names are horizontal sync, vertical sync, horizontal

blank, vertical blank, odd/even field indicator and chromi-

nance flag. Refer to timing diagrams 1, 3 and 4.

SPT

2

SPT2110

3/27/98

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