ADF4106BCP Просмотр технического описания (PDF) - Analog Devices

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ADF4106BCP

PLL Frequency Synthesizer

Analog Devices 

ADF4106

On first applying power to the ADF4106, it needs at three writes

(one each to the R counter latch, the N counter latch and the

function latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control

power-down (CE input) and to detect lock (MUXOUT config-

ured as lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be 166 kHz.

SCLOCK

MOSI

ADuC812

I/O PORTS

SCLK

SDATA

LE ADF4106

CE

MUXOUT

(LOCK DETECT)

Figure 8. ADuC812 to ADF4106 Interface

ADSP-2181 Interface

Figure 9 shows the interface between the ADF4106 and the

ADSP-21xx Digital Signal Processor. The ADF4106 needs a

24-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP-21xx family is to use the

Autobuffered Transmit Mode of operation with Alternate Framing.

This provides a means for transmitting an entire block of serial

data before an interrupt is generated. Set up the word length for

8 bits and use three memory locations for each 24-bit word. To

program each 24-bit latch, store the three 8-bit bytes, enable the

Autobuffered mode and then write to the transmit register of the

DSP. This last operation initiates the autobuffer transfer.

SCLOCK

MOSI

ADSP-21xx TFS

I/O FLAGS

SCLK

SDATA

LE ADF4106

CE

MUXOUT

(LOCK DETECT)

Figure 9. ADSP-21xx to ADF4106 Interface

–18–

REV. 0

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