LTC1325CN Просмотр технического описания (PDF) - Linear Technology
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LTC1325CN Datasheet PDF : 24 Pages
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LTC1325
APPLICATIONS INFORMATION
3. The MSBF bit is set depending on whether the micro-
processor clocks in serial data with MSB- or LSB-first.
4. The DS0 to DS2 bits can be anything except when
entering idle mode or when requesting for ADC read-
ings. In these cases, DS0 to DS2 are set to select the
desired reading: TBAT, VCELL or TAMB.
5. The PS bit should always be 0 so that the LTC1325
does not go into shutdown mode.
6. The DR0 to DR2 should not select any of the test modes.
It may assume different settings between Fast charge
and Top Off charge in order to alter the charging current.
7. The FSCLR bit should be set to 1 to clear any faults and
reset the timer when starting Discharge, Fast charge
or Top Off. The status bits that the LTC1325 returns
during the same I/O operation (that FSCLR is set to 1)
should be checked to determine if faults were indeed
cleared, i.e., discharging or charging has begun. This
is not shown in the simplified flowchart of Figure 6.
For commands other than the START commands,
FSCLR should be set to 0 so as not to reset the timer.
8. The TO0 to TO2 bits should all be set to 1 in discharge
mode to ensure discharge does not end prematurely
due to a timeout fault. During Fast charge or Top Off
charge, these bits are set to a value suitable for the
charge rate used. For example, if the charge rate is 1C,
the timeout period should be set to 80 minutes.
9. In charge mode, the CF capacitor filters the VCELL node
and sees a small ripple due to ripple at the Sense pin.
Prior to taking an ADC reading, the LTC1325 is put in
START
NO CONDITIONING?
YES
START
DISCHARGE
WAIT
START
TOP OFF CHARGE
READ
STATUS
NO
EDV = 1?
YES
START
FAST CHARGE
WAIT
RESUME
FAST CHARGE
IDLE MODE
AND WAIT
READ ADC
AND STATUS
NO
YES
TERMINATE?
WAIT
RESUME
TOP OFF CHARGE
IDLE MODE
READ ADC
AND STATUS
NO
TERMINATE?
YES
IDLE MODE
AND WAIT
MORE
YES
CONDITIONING?
NO
END
LTC1325 • F06
Figure 6. Simple Charging Algorithm
21
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