MC68000P8 Просмотр технического описания (PDF) - Motorola => Freescale

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MC68000P8

Addendum to M68000 User Manual

Motorola => Freescale 

STROBES

AND R/W

36

BR

35

BG

33

CLK

34

39

38

NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA

guarantees their recognition at the next falling edge of the clock.

Figure 11. Bus Arbitration Timing

CLK

47

BR

35

BG

39

AS

LDS/UDDSS

R/W

FC2–FC0

AA2139–A0

33

38

34

36

58

58A

D15D7–D0

NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.

Figure 12. MC68SEC000 Bus Arbitration Timing Diagram

MOTOROLA

M68000 USER’S MANUAL ADDENDUM

17

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