W25M02GWTCIG Просмотр технического описания (PDF) - Winbond

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W25M02GWTCIG

1.8V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS

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4. PIN DESCRIPTIONS

4.1 Serial MCP (SpiStack® ) Device Configuration

W25M02GW

/CS

CLK

W25N01GW

W25N01GW

Die #1

Die #0

W25M02GW (SpiStack® )

DI (IO0)

DO (IO1)

/WP (IO2)

/HOLD (IO3)

Figure 2a. W25M02GW Device Configuration

All signal pins are shared by the stacked dies within the package. Each die is assigned a “Die ID#” in the

factory. Only a single die is active at any given time, and have the control of the SPI bus to communicate

with the external SPI controller. However, all the dies will accept two instructions regardless their Active or

Idle status: 1) “Software Die Select (C2h)” instruction; it is used to set any single die to be active according

to the 8-bit Die ID following the instruction. 2) “Device Reset (FFh)” instruction; it is used to reset all the

stacked dies to their power-up state. Die #0 will always be Active after power-up or Device Reset.

4.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is

deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When

deselected, the devices power consumption will be at standby levels unless an internal erase, program or

write status register cycle is in progress. When /CS is brought low the device will be selected, power

consumption will increase to active levels and instructions can be written to and data read from the device.

After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS

input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure

30b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.

4.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)

The W25M02GW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use

the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising

edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data

or status from the device on the falling edge of CLK.

Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data

to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.

4.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits

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