ADSP-BF539WYBCZ-4A Просмотр технического описания (PDF) - Analog Devices

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ADSP-BF539WYBCZ-4A

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

data, asynchronous packets and control messages. Data is trans-

ferred to or from the synchronous channels through eight DMA

engines that work autonomously from the processor core.

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF539/ADSP-BF539F processor provides a CAN

controller that is a communication controller implementing the

Controller Area Network (CAN) V2.0B protocol. This protocol

is an asynchronous communications protocol used in both

industrial and automotive control systems. CAN is well suited

for control applications due to its capability to communicate

reliably over a network since the protocol incorporates CRC

checking, message error tracking, and fault node confinement.

The CAN controller is based on a 32 entry mailbox RAM and

supports both the standard and extended identifier (ID) mes-

sage formats specified in the CAN protocol specification,

revision 2.0, part B.

Each mailbox consists of eight 16-bit data words. The data is

divided into fields, which includes a message identifier, a time

stamp, a byte count, up to 8 bytes of data, and several control

bits. Each node monitors the messages being passed on the net-

work. If the identifier in the transmitted message matches an

identifier in one of its mailboxes, then the module knows that

the message was meant for it, passes the data into its appropriate

mailbox, and signals the processor of message arrival with an

interrupt.

The CAN Controller can wake up the ADSP-BF539/ADSP-

BF539F processor from Sleep mode upon generation of a

wakeup event, such that the processor can be maintained in a

low power mode during idle conditions. Additionally, a CAN

wakeup event can wake up the on-chip internal voltage regula-

tor from the hibernate state.

The electrical characteristics of each network connection are

very stringent, therefore the CAN interface is typically divided

into 2 parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

ADSP-BF539/ADSP-BF539F CAN module represents the con-

troller part of the interface. This module's network I/O is a

single transmit output and a single receive input, which connect

to a line transceiver.

The CAN clock is derived from the processor system clock

(SCLK) through a programmable divider and therefore does not

require an additional crystal.

MEDIA TRANSCEIVER MAC LAYER (MXVR)

The ADSP-BF539/ADSP-BF539F processor provides a Media

Transceiver (MXVR) MAC layer, allowing the processor to be

connected directly to a MOST® network through just an FOT or

Electrical PHY.

The MXVR is fully compatible with the industry standard stan-

dalone MOST controller devices, supporting 22.579 Mbps or

24.576 Mbps data transfer. It offers faster lock times, greater jit-

ter immunity, a sophisticated DMA scheme for data transfers,

and the high-speed internal interface to the core and L1 mem-

Preliminary Technical Data

ory allows the full bandwidth of the network to be utilized. The

MXVR can operate as either the network master or as a network

slave.

The MXVR supports synchronous data, asynchronous packets,

and control messages using dedicated DMA engines which

operate autonomously from the processor core moving data to

and from L1 memory. Synchronous data is transferred to or

from the synchronous data channels through eight programma-

ble DMA engines. The synchronous data DMA engines can

operate in various modes including modes which trigger DMA

operation when data patterns are detected in the receive data

stream. Furthermore two DMA engines support asynchronous

traffic and a further two support control message traffic.

Interrupts are generated when a user defined amount of syn-

chronous data has been sent or received by the processor or

when asynchronous packets or control messages have been sent

or received.

The MXVR peripheral can wake up the ADSP-BF539/ADSP-

BF539F processor from sleep mode when a wakeup preamble is

received over the network or based on any other MXVR inter-

rupt event. Additionally, detection of network activity by the

MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F

processor from sleep or the hibernate state, and wake up the on-

chip internal voltage regulator from a powered-down state.

These features allow the ADSP-BF539/ADSP-BF539F to operate

in a low-power state when there is no network activity or when

data is not currently being received or transmitted by the

MXVR.

The MXVR clock is provided through a dedicated external crys-

tal or crystal oscillator. For 44.1 KHz frame syncs, use a 45.1584

MHz crystal or oscillator; for 48 KHz frame syncs, use a 49.152

MHz crystal or oscillator. If using a crystal to provide the

MXVR clock, use a parallel-resonant, fundamental mode,

microprocessor-grade crystal.

DYNAMIC POWER MANAGEMENT

The ADSP-BF539/ADSP-BF539F processor provides four oper-

ating modes, each with a different performance/power profile.

In addition, Dynamic Power Management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. When configured for a 0

Volt core supply voltage, the processor enters the hibernate

state. Control of clocking to each of the ADSP-BF539/ADSP-

BF539F processor peripherals also reduces power consumption.

See Table 5 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the powerup default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and sys-

tem clock (SCLK) run at the input clock (CLKIN) frequency. In

Rev. PrF | Page 14 of 68 | September 2006

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