ADSP-BF539(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF539 Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
Table 4. Programmable Flag / GPIO Ports
Peripheral
PPI
SPORT2
SPORT3
SPI0
SPI1
SPI2
UART1
UART2
CAN
MXVR
Alternate Programmable
Flag / GPIO Port Function
PF15–3
PE7–0
PE15–8
PF7–0
PD4–0
PD9–5
PD11–10
PD13–12
PC1–0
PC9–4
The general-purpose I/O pins can be individually controlled by
manipulation of the control and status registers. These pins will
not cause interrupts to be generated to the processor but can be
polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
• GPIO control and status registers – The
ADSP-BF539/ADSP-BF539F processors employ a “write
one to modify” mechanism that allows any combination of
individual GPIO to be modified in a single instruction,
without affecting the level of any other GPIO. Four control
registers and a data register are provided for each GPIO
port. One register is written in order to set GPIO values,
one register is written in order to clear GPIO values, one
register is written in order to toggle GPIO values, and one
register is written in order to specify a GPIO input or out-
put. Reading the GPIO data allows software to determine
the state of the input GPIO pins. PC1 and PC4 are open-
drain when configured as GPIO outputs.
Note that the GP pin is used to specify the status of the GPIO
pins PC9–PC4 at power up. If GP is tied high, then pins
PC9–PC4 are configured as GPIO after reset. The pins cannot
be reconfigured through software, and special care must be
taken with the MLF pin. If the GP pin is tied low, then the pins
are configured as MXVR pins after reset but can be reconfig-
ured as GPIO pins through software.
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF539/ADSP-BF539F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
A/D and D/A converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedi-
cated input clock pin, up to 3 frame synchronization pins, and
up to 16 data pins. The input clock supports parallel data rates
up to fSCLK/2 MHz, and the synchronization signals can be con-
figured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bidirectional
transfer of 8- or 10-bit video data. Additionally, on-chip decode
of embedded start-of-line (SOL) and start-of-field (SOF) pre-
amble packets are supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input Mode – Frame syncs and data are inputs into the PPI.
• Frame Capture Mode – Frame syncs are outputs from the
PPI, but data are inputs.
• Output Mode – Frame syncs and data are outputs from
the PPI.
Input Mode
This mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data and are programmable in the
PPI_CONTROL register.
Frame Capture Mode
This mode allows the video source(s) to act as a slave (e.g., for
frame capture). The ADSP-BF539/ADSP-BF539F processors
control when to read from the video source(s). PPI_FS1 is an
HSYNC output, and PPI_FS2 is a VSYNC output.
Output Mode
This mode is used for transmitting video or other data with up
to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
• Active Video Only Mode
• Vertical Blanking Only Mode
• Entire Field Mode
Active Video Only Mode
This mode is used when only the active video portion of a field
is of interest and not any of the blanking intervals. The PPI will
not read in any data between the end of active video (EAV) and
start of active video (SAV) preamble symbols, or any data
present during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
Rev. A | Page 12 of 60 | February 2008
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