UPD78C11AGF(A)-XXX-3BE Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD78C11AGF(A)-XXX-3BE

8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)

NEC => Renesas Technology 

µPD78C10A(A), 78C11A(A), 78C12A(A)

3. RESET OPERATION

Low-level input to the RESET input causes a system reset, after which the following states occur.

• INTERRUPT ENABLE F/F is reset and the interrupt disable state occurs.

• All interrupt mask registers are set (to “1”) so that all interrupts are masked.

• The interrupt request flag is set (to “0”) so that any pending interrupt is released.

• All PSWs are reset (to “0”).

• 0000H is loaded into the program counter (PC).

• The MODE A register, MODE B register, MODE C register, and MODE F register are set to FFH and the

MM0, MM1, and MM2 bits in the mode control C register and memory mapping register are reset (to

“0”). Port A, Port B, Port C, Port D, and Port F all become input ports (high-impedance output).

• All test flags except the SB flag are reset (to “0”).

• The timer mode register is set to FFH and the timer F/F is reset.

• The timer/event counter’s mode registers (ETMM, EOM) are reset (to “0”).

• The serial interface’s serial mode high register (SMH) is reset (to “0”) and the serial mode low register

(SML) is set to 48H.

• The A/D converter’s A/D channel mode register is reset (to “0”).

• The WR, RD, and ALE signal are set for high impedance.

• Zero cross mode register (ZCM) bits ZC1 and ZC2 are set to “1”.

• The internal timers are initialized.

• The data memory and the contents of the following registers are undefined.

Stack pointer (SP)

Expansion accumulators (EA, EA’) and accumulators (A, A’)

General-purpose registers (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)

Output latch for each port

Timer REG0 and REG1 (TM0, TM1)

Timer/event counter REG0 and REG1 (ETM0, ETM1)

Memory mapping register’s RAE bit

Test flags’ SB flag

When RESET input goes high, the reset state is canceled and program execution begins from address 0000H.

At that point, initialize or reinitialize the various register contents as required by the program.

Table 3-1 lists various hardware states after reset and Table 3-2 lists various pin states after reset.

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