KE5BCCA4M Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5BCCA4M

4,7M Classification CAM

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

4.7M Classification CAM

PRELIMINARY

3. Pin Descriptions

3.1. Pin Assignment

Refer to the datasheet.

3.2. Pin Descriptions

Pin Name

RSTN

CLK

INPMD

PHASE

Description

Attribute Function

Hardware Reset Input

RSTN low resets the device.

Clock

Input

CLK is the clock input. The rising edge of CLK is the timing

reference.

Input Mode

Input

INPMD determines the data input mode. Fix low in high-speed

input mode; fix high in normal speed input mode.

Phase

Input

PHASE determines the action timing of the device in high-speed

input mode. PHASE must be pulled down in normal input mode.

CLKMD

DAT[63:0]

EDAT[7:0]

DATWDT

CNTL[13:0]

SAD

CEN

RWN

Clock Mode

Input

I/O Port

Data Bus

Input/

Output

Tristate

EXTRA Bit Data

Bus

Input/

Output

Tristate

I/O Port Data Bus Input

Width

Control Bus

Input

Sub Address

Input

Device Enable Input

Read/Write

Input

CLKMD determines the CLK input method. Fix low in normal

speed input mode. In high-speed input mode, when supply

single rate clock, fix low and the double rate clock is generated

internally; when supply double rate clock, fix high.

DAT[63:0] is a 64-bit bi-directional data bus for read/write of

CAM memory and registers. RWN controls the bus direction.

EDAT[7:0] is a 8-bit bi-directional data bus for read/write of

EXTRA bits of CAM memory and registers. RWN controls the

bus direction.

DATWDT defines DAT[63:0] width. Fix low to employ all

DAT[63:0]; fix high not to employ DAT[63:32] and to employ

DAT[31:0] with SAD as a substitute for DAT[63:0].

CNTL[13:0] is the 14-bit control bus to control the device. The

search operations, the command assertions, and the register

accesses are invoked corresponding to CNTL[13:0].

SAD assigns DAT[31:0] to internal 64-bit data bus when

DAT[63:32] is unused (DATWDT=high). When SAD is low,

DAT[31:0] is assigned to lower 32-bit; when high, it is assigned

to upper 32-bit.

CEN low invokes operations such as read/write, search and

command.

RWN determines the direction of the I/O Port data bus

DAT[63:0] and that of the EXTRA bit data bus EDAT[7:0]. RWN

low selects a write cycle and RWN high selects a read cycle.

OEDATN

I/O Port Data Bus Input

Output Enable

OEDATN is output enable signal for DAT[63:0] and EDAT[7:0].

Version 2.3.8

4

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