HFA3860 Просмотр технического описания (PDF) - Intersil

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HFA3860

11 Mbps Direct Sequence Spread Spectrum Baseband Processor

Intersil 

TX_PE

tD1

IOUT, QOUT

TXRDY

TX_CLK

TXD

HFA3860

tPEH

tTCD tTCD

tRC

tTDS

tTDH

FIGURE 21. TX PORT SIGNAL TIMING

tTLP

tME

tRI

RX_PE

IIN, QIN

MD_RDY

RX_CLK

RXD

CCA, RSSI

tRLP

tRD3

tREH

tRCP

tRD2

tCCA

tRCD tRCD

tRD1 tRDD tRDS

NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output on TEST (5:0).

FIGURE 22. RX PORT SIGNAL TIMING

MCLK

tD2

TEST 0-7, CCA, ANTSEL, TEST_CK

RESET

tRPW

MCLK

tCP

NOTE: Delays will occur from rising or falling edige of MCLK if CR2 Bit 7 is set to a 1.

FIGURE 23. MISCELLANEOUS SIGNAL TIMING

4-39

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