Z80180_ Просмотр технического описания (PDF) - Zilog

Номер в каталоге

Компоненты Описание

производитель

Z80180_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

24

1st Op Code 2nd Op Code Displacement

Fetch Cycle Fetch Cycle Read Cycle

CPU internal

Operation

Memory

Next instruction

Write Cycle Fetch Cycle

T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T1 T1 T1 T2 T3 T1 T2

Phi

A0–A19

D0–D7

M1

MREQ

RD

PC

(DDH)

PC+1

(7OH–77H)

PC+2

d

IX+d

g

PC+3

WR

Machine Cycle

MC1

MC2

NOTE: d = displacement

g = register contents

MC3 MC4 MC5 MC6 MC7

Figure 14. Instruction Timing Diagram

This instruction moves the contents of a CPU register (g) to the memory

location with address computed by adding a signed 8-bit displacement (d)

to the contents of an index register (IX).

The instruction cycle begins with the two machine cycles to read the two

byte instruction Op Code as indicated by M1 Low. Next, the instruction

operand (d) is fetched.

UM005001-ZMP0400

Share Link: