Z80181_ Просмотр технического описания (PDF) - Zilog

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производитель

Z80181_

Family MPU

Zilog 

Z 8018x Fam ily

M PU Us e r M anual

21

Phi

A0–A19

Wait States (TW) are inserted as previously described for Op Code fetch

cycles. Figure 11 illustrates the read/write timing without Wait States

(Tw), while Figure 12 illustrates read/write timing with Wait States (TW).

Read Cycle

T1

T2

T3

Write Cycle

T1

T2

T3

T1

Memory address

Memory address

D0–D7

WAIT

MREQ

RD

WR

Read data

Write data

Figure 11. Memory Read/Write (without Wait State) Timing Diagram

UM005001-ZMP0400

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