PCF8564ACX9 Просмотр технического описания (PDF) - NXP Semiconductors.

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PCF8564ACX9

Real time clock and calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8564A

Real time clock and calendar

9. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 12).

SDA

SCL

Fig 12. Bit transfer

data line

stable;

data valid

change

of data

allowed

mbc 621

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the

STOP condition (P), see Figure 13.

SDA

SDA

SCL

S

START condition

Fig 13. Definition of START and STOP conditions

P

STOP condition

SCL

mbc 622

9.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 14).

PCF8564A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 30 September 2010

© NXP B.V. 2010. All rights reserved.

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