EV-ADF4196SD1Z Просмотр технического описания (PDF) - Analog Devices
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EV-ADF4196SD1Z Datasheet PDF : 28 Pages
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Data Sheet
ADF4196
SPECIFICATIONS
AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V;
RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range = −40°C to +85°C.
Table 1.
Parameter
Min
RF CHARACTERISTICS
RF Input Frequency (RFIN±)
0.4
RF Input Sensitivity
−10
Maximum Allowable Prescaler Output
Frequency1
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Edge Slew Rate
300
REFIN Input Sensitivity
0.7
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
ICP Up/Down
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP Up vs. Down Matching
ICP vs. VCP
ICP vs. Temperature
DIFFERENTIAL AMPLIFIER
Input Current
Output Voltage Range
VCO Tuning Range
Output Noise
LOGIC INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IINH, IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
DVDD1, DVDD2, DVDD3
VP1, VP2
VP3
IDD (AVDD + DVDD1, DVDD2, DVDD3 +
SDVDD)
IDD (VP1 + VP2)
IDD (VP3)
IDD Power-Down
1
1.4
1.8
1.4
VDD − 0.4
2.7
4.5
5.0
Typ
6.6
104
5
1
0.1
1
1
1
7
AVDD
22
22
24
10
Max
Unit
Test Conditions/Comments
6
GHz
See Figure 21 for input circuit
0
dBm
750
MHz
300
VDD
0 to VDD
10
±100
26
MHz
V/µs
V p-p
V
pF
µA
MHz
For f > 120 MHz, set REF/2 bit = 1 (Register R1)
AC-coupled
CMOS compatible
mA
RSET = 2.4 kΩ
µA
RSET = 2.4 kΩ
%
4
kΩ
Nominally RSET = 2.4 kΩ
nA
%
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
%
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
%
0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
VP3 − 0.3
VP3 − 0.8
nA
V
V
nV/√Hz
At 20 kHz offset
V
0.7
V
±1
µA
10
pF
V
IOH = 500 µA
0.4
V
IOL = 500 µA
3.3
V
V
5.5
V
AVDD ≤ VP1, VP2 ≤ 5.5 V
5.65
V
VP1, VP2 ≤ VP3 ≤ 5.65 V
27
mA
27
mA
30
mA
µA
Rev. D | Page 3 of 28
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