AD9848AKST Просмотр технического описания (PDF) - Analog Devices
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AD9848AKST Datasheet PDF : 32 Pages
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Accessing a Double-Wide Register
There are many double-wide registers in the AD9848/AD9849,
for example, oprmode, clpdmtog1_0, and clpdmscp3, and so
on. These registers are configured into two consecutive 6-bit
registers with the least significant six bits located in the lower of
the two addresses and the remaining most significant bits
located in the higher of the two addresses. For example, the
six LSBs of the clpdmscp3 register, clpdmscp3[5:0], are
located at Address 0x81. The most significant six bits of the
clpdmscp3 register, clpdmscp3[11:6], are located at Address 0x82.
The following rules must be followed when accessing double-
wide registers:
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
AD9848/AD9849
clpdmscp3 register, the contents of Address 0x81 must
be written first followed by the contents of Address 0x82.
The register will be updated after the completion of the
write to Register 0x82, either at the next SL rising edge
or next VD/HD falling edge.
3. A single write to the lower of the two consecutive ad-
dresses of a double-wide register that is not followed by
a write to the higher address of the registers is not per-
mitted. This will not update the register.
4. A single write to the higher of the two consecutive ad-
dresses of a double-wide register that is not preceded by
a write to the lower of the two addresses is not permit-
ted. Although the write to the higher address will
update the full double-wide register, the lower six bits
of the register will be written with an indeterminate
value if the lower address was not written first.
Address
Bit
Content Width
AFE Registers # Bits 56
00
[5:0]
6
01
[1:0]
2
02
[5:0]
6
03
[3:0]
4
04
[5:0]
6
05
[1:0]
2
06
[5:0]
6
07
[5:0]
6
08
[5:0]
6
09
[5:0]
6
0A
[5:0]
6
Default
Value Register Name
00
oprmode[5:0]
00
oprmode[7:6]
16
ccdgain[5:0]
02
ccdgain[9:6]
00
refblack[5:0]
02
refblack[7:6]
00
ctlmode
00
pxga gain0
00
pxga gain1
00
pxga gain2
00
pxga gain3
Register Description
AFE Operation Mode (See AFE Register Breakdown)
VGA Gain
Black Clamp Level
Control Mode (See AFE Register Breakdown)
PxGA Color 0 Gain
PxGA Color 1 Gain
PxGA Color 2 Gain
PxGA Color 3 Gain
Miscellaneous/Extra # Bits 26
0F
[5:0]
6
00
16
[0]
1
00
17
[5:0]
6
00
18
[5:0]
6
00
19
[0]
1
00
1B
[5:0]
6
00
1C
[0]
1
00
1D
[0]
1
00
1E
[0]
1
01
1F
[0]
1
00
20
[5:0]
6
00
26
[0]
1
00
INITIAL2
out_cont
update[5:0]
update[11:6]
preventupdate
doutphase
disablerestore
vdhdpol
fieldval
hblkretime
INITIAL1
tgcore_rstb
See Recommended Power-Up Sequence Section. Should be
set to “4” decimal (000100).
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control. Sets the line within the field
for serial data update to occur.
Prevent the Update of the “VD/HD Updated” Registers
DOUT Phase Control
Disable CCDIN DC Restore Circuit during PBLK
(1 = Disable)
VD/HD Active Polarity (0 = Low Active, 1 = High Active)
Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
Re-Sync hblk to h1 Clock
See Recommended Power-Up Sequence Section. Should be
set to “53” decimal (110101).
TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
REV. A
–13–
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