HD6433024F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

Номер в каталоге

Компоненты Описание

производитель

HD6433024F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

D.2 Pin States at Reset

Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an

external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the

input state. AS, RD, HWR, LWR, and CS0 go high, and D15 to D0 go to the high-impedance state.

The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES

is sampled. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.

P67/φ

Access to external

memory

T1 T2 T3

RES

Internal reset

signal

A19 to A0

H'00000

CS0

AS, RD

(read)

HWR, LWR

(write)

D15 to D0

(write)

High impedance

I/O port,

CS7 to CS1

High impedance

Figure D.1 Reset during Memory Access (Modes 1 and 2)

778

Share Link: