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IR3871MPBF

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

International Rectifier 

LAYOUT RECOMMENDATION

Bypass Capacitor:

One 1µF high quality ceramic capacitor should be

placed as near VCC pin as possible. The other

end of capacitor can be connected to a via or

connected directly to GND plane. Use a GND

plane instead of a thin trace to the GND pin

because a thin trace have too much impedance.

Boot Circuit:

CBOOT should be placed near the BOOT and

PHASE pins to reduce the impedance when the

upper MOSFET turns on.

Power Stage:

Figure 24 shows the current paths and their

directions for the on and off periods. The on time

path has low average DC current and high AC

current. Therefore, it is recommended to place the

input ceramic capacitor, upper, and lower

MOSFET in a tight loop as shown in Figure 24.

The purpose of the tight loop from the input

ceramic capacitor is to suppress the high

frequency (10MHz range) switching noise and

reduce Electromagnetic Interference (EMI). If this

path has high inductance, the circuit will cause

voltage spikes and ringing, and increase the

switching loss. The off time path has low AC and

high average DC current. Therefore, it should be

laid out with a tight loop and wide trace at both

ends of the inductor. Lowering the loop resistance

reduces the power loss. The typical resistance

value of 1-ounce copper thickness is 0.5mΩ per

square inch.

IR3871MPBF

VIN

ON

Q1

VOUT

IR3871

OFF

CIN

Q2

COUT

Figure 24. Current Path of Power Stage

17

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