DS26334 Просмотр технического описания (PDF) - Maxim Integrated

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DS26334

3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul Line Interface Unit

Maxim Integrated 

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

Figure 5-4. Interrupt Handling Flow Diagram

Interrupt Allowed

No

Interrupt Conditon

Exist?

Yes

Read Interrupt Status

Register

Read Corresponding Status

Register (Optional)

Service the Interrupt

5.2 Power-Up and Reset

Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values.

Writing to the Software Reset Register (SWR) generates at least 1µs reset cycle, which has the same effect as the

power-up reset.

The DS26334 can be reset by a low going pulse on the RSTB pin (see Table 4-1). A reset can also be performed in

software by writing any value to the SWR register.

5.3 Master Clock

The DS26334 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK

as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS transmission uses

MCLK for transmit all ones condition. See register MC to set desired incoming frequency. When the PLLE bit is set,

the master clock adapter will generate both 2.048MHz (E1) and 1.544MHz (T1) clocks. If the PLLE bit is clear, both

internal reference clocks will track MCLK.

MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register CCR is used to select the clock

generated for CLKA and the TECLK. Any RCLK can also be selected as an input to the clock generator using this

same register. For a detailed description of selections available see Figure 5-5.

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