X28HC64 Просмотр технического описания (PDF) - Renesas Electronics

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X28HC64

64k, 8k x 8-Bit 5 Volt, Byte Alterable EEPROM

Renesas Electronics 

X28HC64

ADDRESS

CE

OE

WE

DATA IN

DATA OUT

tWC

tAS

tAH

tCW

tOES

tOEH

tCS

tCH

tDV

DATA VALID

tDS

tDH

HIGH Z

FIGURE 16. CE CONTROLLED WRITE CYCLE

OE

Note 17

CE

WE

tWP

tBLC

tWPH

ADDRESS

Note 18

I/O

LAST BYTE

Byte 0

Byte 1

Byte 2

Byte n

Byte n+1

*For each successive write within the page write operation, A6–A12 should be the same or

writes to an unknown address could occur.

Byte n+2

tWC

NOTES:

FIGURE 17. PAGE WRITE CYCLE

17. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from

another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.

18. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE

or WE controlled write cycle timing.

FN8109 Rev 4.00

June 27, 2016

Page 13 of 18

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