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WM8912 Просмотр технического описания (PDF) - Cirrus Logic

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WM8912 Datasheet PDF : 129 Pages
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WM8912
SLAVE MODE
Production Data
Figure 3 Audio Interface Timing – Slave Mode
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25oC, Slave Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Interface Timing - Slave Mode
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDS
MIN
TYP
MAX
50
20
20
20
10
10
20
UNIT
ns
ns
ns
ns
ns
ns
ns
Note: BCLK period must always be greater than or equal to MCLK period.
w
PD, Rev 4.1, February 2013
16

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