WM8581AGEFT Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8581AGEFT

Multichannel CODEC with S/PDIF Transceiver

Wolfson Microelectronics plc 

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WM8581

CONTROL INTERFACE OPERATION

Control of the WM8581 is implemented either in Hardware Control Mode or Software Control Mode.

The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low,

Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected.

The Software Control Interface is described below and Hardware Control Mode is described on page

75.

Software control is implemented with a 3-wire (3-wire write, 4-wire read, SPI compatible) or 2-wire (2-

wire write, 2-wire read) serial interface.

The interface configuration is determined by the state of the SWMODE pin. If the SWMODE pin is

low, the 2-wire configuration is selected. If SWMODE is high the 3-wire SPI compatible configuration

is selected.

HWMODE

0

1

Software Control Hardware Control

SWMODE

0

1

2-wire control 3-wire control

Table 8 Hardware/Software Mode Setup

The control interface is 5V tolerant, meaning that the control interface input signals CSB, SCLK and

SDIN may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by

DVDD.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE WITH READ-BACK

SDIN is used to program data, SCLK is used to clock in the program data and CSB is used to latch

the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write protocol is

shown in Figure 6.

Figure 6 3-Wire SPI Compatible Interface

1. A[6:0] are Control Address Bits

2. D[8:0] are Control Data Bits

3. CSB is edge sensitive – the data is latched on the rising edge of CSB.

REGISTER READ-BACK

The read-only status registers can be read back via the SDO pin. To enable readback the READEN

control register bit must be set. The status registers can then be read using one of two methods,

selected by the CONTREAD register bit.

With CONTREAD set, a single read-only register can be read back by writing to any other register or

to a dummy register. The register to be read is determined by the READMUX[2:0] bits. When a write

to the device is performed, the device will respond by returning the status byte in the register selected

by the READMUX register bits. This 3-wire interface read back method using a write access is shown

in.Figure 7

w

PD Rev 4.0 April 2007

21

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